SNVSCB5B March   2022  – May 2025 TPS388R0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I2C
      2. 7.3.2 Auto Mask (AMSK)
      3. 7.3.3 PEC
      4. 7.3.4 VDD
      5. 7.3.5 MON
      6. 7.3.6 NIRQ
      7. 7.3.7 NRST
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS38800-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1 Overview

The TPS38800-Q1 family of devices has up to 8 channels that can be configured for over voltage, under voltage or both in a window configuration. Fault outputs can be selectively mapped to NIRQ pin. The TPS38800-Q1 features highly accurate window threshold voltages (up to ±6 mV) and a variety of voltage thresholds which can be factory configured or set on boot up by I2C commands.

The TPS388R0-Q1 family of devices has up to 6 channels that can be configured for over voltage, under voltage or both in a window configuration. Fault outputs can be selectively mapped to NIRQ and/or NRST pin. The TPS388R0-Q1 features highly accurate window threshold voltages (up to ±6 mV) and a variety of voltage thresholds which can be factory configured or set on boot up by I2C commands.

The TPS38800-Q1/TPS388R0-Q1 includes the resistors used to set the overvoltage and undervoltage thresholds internal to the device. These internal resistors allow for lower component counts and greatly simplifies the design because no additional margins are needed to account for the accuracy of external resistors.

The TPS38800-Q1 is designed to assert active low output signals (NIRQ) when the monitored voltage is outside the safe window. The TPS388R0-Q1 is designed to assert active low output signals (NIRQ/NRST) when the monitored voltage is outside the safe windowThe factory configuration can have the interrupts disabled for over voltage and under voltage faults, sequence timeout, BIST enabled at POR, and over voltage and under voltage deglitch settings depending on the OTP