SNVSCB5B March   2022  – May 2025 TPS388R0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I2C
      2. 7.3.2 Auto Mask (AMSK)
      3. 7.3.3 PEC
      4. 7.3.4 VDD
      5. 7.3.5 MON
      6. 7.3.6 NIRQ
      7. 7.3.7 NRST
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS38800-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

At 2.6V ≤ VDD ≤ 5.5V, NIRQ,NRST Voltage  = 10kΩ to VDD, NIRQ,NRST load = 10pF, and over the operating free-air temp range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3V.
MIN NOM MAX UNIT
COMMON PARAMETERS
tBIST POR to ready with BIST, TEST_CFG.AT_POR=1 includes OTP load 12 ms
tNBIST POR to ready without BIST, TEST_CFG.AT_POR=0 includes OTP load 2 ms
BIST BIST time,TEST_CFG.AT_POR=1 or TEST_CFG.AT_SHDN=1 10 ms
tI2C_ACT I2C active from BIST complete 0 µs
tSEQ_Range Sequence timestamp range, ACT or SLEEP edge to max counter 4 s
tSEQ_LSB Sequence timestamp resolution 50 µs
tMON_ACT Monitoring active from ACT rising edge 10 µs
tNIRQ Fault detection to NIRQ assertion latency (except OV/UV faults) 25 µs
tPD_NIRQ_1X HF fault Propagation detect delay (default deglitch filter) includes digitial delay VIT_OV/UV +/- 100mV 650 ns
tPD_NIRQ_4X HF fault Propagation detect delay (default deglitch filter) includes digitial delay VIT_OV/UV +/- 400mV 750 ns
tNRST Fault detection to NRST assertion latency (except OV/UV faults) 25 µs
tPD_NRST_1X HF fault Propagation detect delay (default deglitch filter) includes digitial delay VIT_OV/UV +/- 100mV 650 ns
tPD_NRST_4X HF fault Propagation detect delay (default deglitch filter) includes digitial delay VIT_OV/UV +/- 400mV 750 ns
tSEQ_ACC Accuracy of sequence timestamp -5 5 %
tD RESET  time delay I2C Register  time delay =000 200 µs
I2C Register  time delay =001 1 ms
I2C Register  time delay =010 10 ms
I2C Register  time delay =011 16 ms
I2C Register  time delay =100 20 ms
I2C Register  time delay =101 70 ms
I2C Register time delay =110 100 ms
I2C Register  time delay =111 200 ms
tGI_R UV & OV debounce range via I2C FLT_HF(N) 0.1 102.4 µs
I2C TIMING CHARACTERISTICS
fSCL Serial clock frequency Standard mode 100 kHz
fSCL Serial clock frequency Fast mode 400 kHz
fSCL Serial clock frequency Fast mode + 1 MHz
tLOW SCL low time Standard mode 4.7 µs
tLOW SCL low time Fast mode 1.3 µs
tLOW SCL low time Fast mode + 0.5 µs
tHIGH SCL high time Standard mode 4 µs
tHIGH SCL high time Fast mode + 0.26 µs
tSU;DAT Data setup time Standard mode 250 ns
tSU;DAT Data setup time Fast mode 100 ns
tSU;DAT Data setup time Fast mode + 50 ns
tHD;DAT Data hold time Standard mode 10 3450 ns
tHD;DAT Data hold time Fast mode 10 900 ns
tHD;DAT Data hold time Fast mode + 10 ns
tSU;STA Setup time for a Start or Repeated Start condition Standard mode 4.7 µs
tSU;STA Setup time for a Start or Repeated Start condition Fast mode 0.6 µs
tSU;STA Setup time for a Start or Repeated Start condition Fast mode + 0.26 µs
tHD:STA Hold time for a Start or Repeated Start condition Standard mode 4 µs
tHD:STA Hold time for a Start or Repeated Start condition Fast mode 0.6 µs
tHD:STA Hold time for a Start or Repeated Start condition Fast mode + 0.26 µs
tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs
tBUF Bus free time between a STOP and START condition Fast mode 1.3 µs
tBUF Bus free time between a STOP and START condition Fast mode + 0.5 µs
tSU;STO Setup time for a Stop condition Standard mode 4 µs
tSU;STO Setup time for a Stop condition Fast mode 0.6 µs
tSU;STO Setup time for a Stop condition Fast mode + 0.26 µs
trDA Rise time of SDA signal Standard mode 1000
trDA Rise time of SDA signal Fast mode 20 300 ns
trDA Rise time of SDA signal Fast mode + 120 ns
tfDA Fall time of SDA signal Standard mode 300 ns
tfDA Fall time of SDA signal Fast mode 1.4 300 ns
tfDA Fall time of SDA signal Fast mode + 6.5 120 ns
trCL Rise time of SCL signal Standard mode 1000 ns
trCL Rise time of SCL signal Fast mode 20 300 ns
trCL Rise time of SCL signal Fast mode + 120 ns
tfCL Fall time of SCL signal Standard mode 300 ns
tfCL Fall time of SCL signal Fast mode 6.5 300 ns
tfCL Fall time of SCL signal Fast mode + 6.5 120 ns
tSP Pulse width of SCL and SDA spikes that are suppressed Standard mode, Fast mode and Fast mode + 50 ns