SPRACE5A May   2019  – May 2021 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

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Migrating From eCAN

This section provides some helpful hints if you are migrating from the eCAN module to the DCAN module. DCAN follows a very different register structure compared to eCAN and hence code written for one module cannot be migrated to another. The following section highlights the differences, but also illustrates the functional similarities between the two modules.

The following features are available in DCAN that are not available in eCAN:

  • Parity check mechanism for all RAM modules.
  • Automatic Retransmission (upon loss of arbitration) can be disabled.
  • Silent mode (Node listens passively).
  • Mailbox RAM may be combined to form FIFO buffers.
  • Data can be monitored on CANTX pin in self-test mode.

The following are the features that are available in eCAN that are not available in DCAN:

  • Timestamping of messages.
  • Transmission priority configuration (TPL).
  • Data-byte order configuration (DBO).
  • Direct access to the mailbox RAM by the CPU - In DCAN, mailbox RAM is accessed through the Interface (IFx) registers. The IFx registers may be thought of as a "window" through which the mailbox RAM is accessed.

Table 4-2 shows the equivalent registers and bit-fields in eCAN and DCAN and also some functional differences.

Table 4-2 eCAN-DCAN Registers and Bits Equivalence
FunctioneCANDCANComments
CAN module software reset bitCANMC.SRESCAN_CTL.SWR
Automatic bus-on (after bus-off)CANMC.ABOCAN_CTL.ABO
Self-test modeCANMC.STMCAN_CTL.TestFurther selection needed for DCAN in CAN_TEST register
Configuration modeCANMC.CCRCAN_CTL.Init
Configuration mode enabledCANES.CCECAN_CTL.CCE
Mailbox interrupt sourceCANGIFx.MIVyCAN_INT.INTnID
Interrupt line selection (for mailbox)CANMILCAN_IP_MUX21
Interrupt line selection (for error & status)CANGIM.GILHardwired to CANINT0
CAN to PIE interrupt line0 enableCANGIM.I0ENCAN_CTL.IE0
CAN to PIE interrupt line1 enableCANGIM.I1ENCAN_CTL.IE1
Transmit Error CounterCANTEC.TECCAN_ERRC.TEC
Receive Error CounterCANREC.RECCAN_ERRC.REC
Bus-off statusCANES.BOCANES.Boff
Early warning (TEC or REC = 96)CANES.EWCANES.EWarn
Error passiveCANES.EPCANES.EPass
Acceptance mask registerLAMCAN_IFxMSK
Acceptance mask filter for a MailboxLAM.LAMCAN_IFnMSK.MskMask bit behavior is opposite
Mailbox message-ID registerMSGIDCAN_IF1ARB
Mailbox enable or disableCANME.MEnCAN_IFnARB.MsgValIn DCAN, MBX can remain "enabled" while configuring the MSGID.
Extended IdentifierMSGID.IDECAN_IFxARB.Xtd
Mailbox directionCANMD.MDnCAN_IFxARB.Dir
Message IDMSGID.IDCAN_IFxARB.Id
Lost message indicationCANRML.RMLnCAN_IFxMCTL.MsgLst
Transmission requestCANTRS.TRSnCAN_IFxMCTL.TxRqst
# of bytes in a frameMSGCTRL.DLCCAN_IFxMCTL.DLC
Transmit or Receive priorityHigher numbered MBX has priorityLower numbered MBX has priority
Enabling/disabling interrupts for a specific mailbox CANMIM IFnMCTL.TxIE or IFnMCTL.RxIE