SPRAD06C March   2022  – March 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  DBI
    8. 2.8  VPP
    9. 2.9  Net Classes
    10. 2.10 DDR4 Signal Termination
    11. 2.11 VREF Routing
    12. 2.12 VTT
    13. 2.13 POD Interconnect
    14. 2.14 CK and ADDR_CTRL Topologies and Routing Guidance
    15. 2.15 Data Group Topologies and Routing Guidance
    16. 2.16 CK and ADDR_CTRL Routing Specification
      1. 2.16.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.16.2 CK and ADDR_CTRL Routing Limits
    17. 2.17 Data Group Routing Specification
      1. 2.17.1 DQLM - DQ Longest Manhattan Distance
      2. 2.17.2 Data Group Routing Limits
    18. 2.18 Bit Swapping
      1. 2.18.1 Data Bit Swapping
      2. 2.18.2 Address and Control Bit Swapping
  6. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  LPDDR4 DBI
    8. 3.8  Net Classes
    9. 3.9  LPDDR4 Signal Termination
    10. 3.10 LPDDR4 VREF Routing
    11. 3.11 LPDDR4 VTT
    12. 3.12 CK0 and ADDR_CTRL Topologies
    13. 3.13 Data Group Topologies
    14. 3.14 CK0 and ADDR_CTRL Routing Specification
    15. 3.15 Data Group Routing Specification
    16. 3.16 Byte and Bit Swapping
  7. 4LPDDR4 Board Design Simulations
    1. 4.1 Board Model Extraction
    2. 4.2 Board-Model Validation
    3. 4.3 S-Parameter Inspection
    4. 4.4 Time Domain Reflectometry (TDR) Analysis
    5. 4.5 System Level Simulation
      1. 4.5.1 Simulation Setup
      2. 4.5.2 Simulation Parameters
      3. 4.5.3 Simulation Targets
        1. 4.5.3.1 Eye Quality
        2. 4.5.3.2 Delay Report
        3. 4.5.3.3 Mask Report
    6. 4.6 Design Example
      1. 4.6.1 Stack-Up
      2. 4.6.2 Routing
      3. 4.6.3 Model Verification
      4. 4.6.4 Simulation Results
  8. 5Additional Information: Package Delays
  9. 6Summary
  10. 7References
  11. 8Revision History

3.15 Data Group Routing Specification

Skew within the Byte signal net class directly reduces the setup and hold margin for the DQ and DM nets. Thus, as with the ADDR_CTRL signal net class and associated CK0 clock net class, this skew must be controlled. Per-bit deskew capability within the PHY substantially loosens the skew tolerance requirements. The skew budgets in Table 3-7 include total delay from SoC die pad to DRAM pin. (that is, delay of SOC package and PCB). Package delays are provided in Additional Information: Package Delays. The designer is free to length match using smaller tolerance than the values shown in Table 3-7. The routed PCB track has a delay proportional to the length. Thus, the length skew must be managed through matching the lengths of the routed tracks within a defined group of signals. The only way to practically match lengths on a PCB is to lengthen the shorter traces. Consider Z-axis delays (VIAs) with accurate stackup information during analysis.

Note: TI does not require nor recommend to match the lengths across all byte lanes. Length matching is only required within each byte.

Table 3-7 contains the routing specifications for the Byte0 and Byte1 routing groups. Each signal net class and the associated clock net class is routed and matched independently.

Table 3-7 Data Group Routing Specifications
Number Parameter MIN TYP MAX UNIT
LP4_DRS1 Propagation delay of net class DQSx (RSD1) 450(1) ps
LP4_DRS2 Propagation delay of net class BYTEx (RSD2) 450(1) ps
LP4_DRS3 Difference in propagation delays of CK0 pair and each DQS pair.
(RSAC1 - RSD1) (2)		 0(3)(4) 3(3)(4) tCK
LP4_DRS4 Skew within net class DQSx.
Skew of DDR0_DQSx and DDR0_DQSx_n (RSD1)		 1.5(4)(6) ps
LP4_DRS5 Skew across DQSx and BYTEx net classes.
(Skew of RSD1 and RSD2) (7)		 150(3)(4) ps
LP4_DRS6 Difference in propagation delays of shortest DQ/DM bit in BYTEx and respective DQSx.
(RSD2 - RSD1)(8)		 -49(3)(4)(5) ps
LP4_DRS7 Vias Per Trace 2(1) vias
LP4_DRS8 VIA Stub Length 40 Mils
LP4_DRS9 Via Count Difference 0(9) vias
LP4_DRS10 RSD1 center-to-center spacing (between different clock net classes) 5w(10)
LP4_DRS11 RSD1 center-to-center spacing (within clock net class)(11) See note below
LP4_DRS12 RSD2 center-to-center spacing (between different signal net classes/bytes) 5w(10)
LP4_DRS13 RSD2 center-to-center spacing (to self or within signal net class) 3w(10)
(1) Max value is based upon conservative signal integrity approach. FR4 material assumed with Dk ≃ 3.7 - 3.9 and Df ≃ 0.002. This value can be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) Propagation delay of CK0 pair must be greater than propagation delay of each DQS pair.
(3) Simulation(12) must be performed and the delay report analyzed to make sure delays are within the limit. Delay reports from PCB layout tools use a simplified calculation based on a constant propagation velocity factor. TI recommends initially delay matching in PCB layout tool to a target less than 20% of the limit.
(4) Consider the delays from SOC die pad to the DRAM pin (that is, delays of SOC package and delays of PCB up to the DRAM pin. DRAM package delays are omitted). Refer to Additional Information: Package Delays.
(5) Recommend that the propagation delay of DQS is shorter than all DQx within a byte. If that is not possible, then LP4_DRS6 specifies that a DQ can be shorter by at most 49ps.
(6) Recommendation for PCB layout tool design. Required to be verified by simulation(12), confirm JEDEC defined Vix_DQS_ratio (20%) and Vix_CK_ratio (25%) are satisfied, also confirm good eye margins.
(7) Skew matching is only done within a byte including DQS. Skew matching across bytes is neither required nor recommended.
(8) Propagation delay of the shortest DQ, DM bit in BYTEx Signal Net Class is recommended to be greater than the propagation delay of the respective DQSx.
(9) VIA count difference can increase by 1 only if accurate 3-D modeling of the signal flight times. This includes accurately modeled signal propagation through VIA. This has been applied to make sure skew maximums are not exceeded.
(10) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints). Spacing minimums can be relaxed if simulations(12) accurately capture crosstalk between neighboring victim and aggressor traces and show good margin. Consider VIA spacing. Signals with adjacent VIAs near SOC must not also have adjacent VIAs near the DRAM.
(11) DQS pair spacing is set to make sure of proper differential impedance. For example, the P to N spacing set is to make sure of proper differential impedance. The designer must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing must be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer. Refer to impedance targets in Section 1.3.
(12) Simulation refers to a power-aware IBIS Signal Integrity (SI) simulation. Simulate across process, voltage, and temperature (PVT).