SPRAD06C March   2022  – March 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  DBI
    8. 2.8  VPP
    9. 2.9  Net Classes
    10. 2.10 DDR4 Signal Termination
    11. 2.11 VREF Routing
    12. 2.12 VTT
    13. 2.13 POD Interconnect
    14. 2.14 CK and ADDR_CTRL Topologies and Routing Guidance
    15. 2.15 Data Group Topologies and Routing Guidance
    16. 2.16 CK and ADDR_CTRL Routing Specification
      1. 2.16.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.16.2 CK and ADDR_CTRL Routing Limits
    17. 2.17 Data Group Routing Specification
      1. 2.17.1 DQLM - DQ Longest Manhattan Distance
      2. 2.17.2 Data Group Routing Limits
    18. 2.18 Bit Swapping
      1. 2.18.1 Data Bit Swapping
      2. 2.18.2 Address and Control Bit Swapping
  6. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  LPDDR4 DBI
    8. 3.8  Net Classes
    9. 3.9  LPDDR4 Signal Termination
    10. 3.10 LPDDR4 VREF Routing
    11. 3.11 LPDDR4 VTT
    12. 3.12 CK0 and ADDR_CTRL Topologies
    13. 3.13 Data Group Topologies
    14. 3.14 CK0 and ADDR_CTRL Routing Specification
    15. 3.15 Data Group Routing Specification
    16. 3.16 Byte and Bit Swapping
  7. 4LPDDR4 Board Design Simulations
    1. 4.1 Board Model Extraction
    2. 4.2 Board-Model Validation
    3. 4.3 S-Parameter Inspection
    4. 4.4 Time Domain Reflectometry (TDR) Analysis
    5. 4.5 System Level Simulation
      1. 4.5.1 Simulation Setup
      2. 4.5.2 Simulation Parameters
      3. 4.5.3 Simulation Targets
        1. 4.5.3.1 Eye Quality
        2. 4.5.3.2 Delay Report
        3. 4.5.3.3 Mask Report
    6. 4.6 Design Example
      1. 4.6.1 Stack-Up
      2. 4.6.2 Routing
      3. 4.6.3 Model Verification
      4. 4.6.4 Simulation Results
  8. 5Additional Information: Package Delays
  9. 6Summary
  10. 7References
  11. 8Revision History

5 Additional Information: Package Delays

The package delays provided in this appendix are measured from SOC die pad to SOC package pin. The skew limits specified in Table 3-6 and Table 3-7 are measured from SOC die pad to DRAM package pin (including these delays inside the SOC package). The designer can sum these package delays with the PCB delays for each net when checking for compliance with the skew limits. Simulations of the propagation delays are then required to confirm the delays satisfy the requirements.

PROCESSOR PIN NAME AM62x ALW PACKAGE DELAY (ps) AM62x AMC PACKAGE DELAY (ps) AM62Lx ANB PACKAGE DELAY (ps) NET CLASS DESCRIPTION
DDR0_A0 21.00 28.55 13.44 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A1 19.94 26.82 15.17 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A2 16.13 26.60 10.20 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A3 11.28 26.33 19.40 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A4 11.62 26.52 22.22 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A5 20.98 26.43 15.29 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_A6 17.04 33.55 18.29 ADDR_CTRL Used with DDR4
DDR0_A7 19.08 31.69 6.79 ADDR_CTRL Used with DDR4
DDR0_A8 21.55 34.42 15.59 ADDR_CTRL Used with DDR4
DDR0_A9 13.33 34.25 19.06 ADDR_CTRL Used with DDR4
DDR0_A10 10.71 32.94 12.39 ADDR_CTRL Used with DDR4
DDR0_A11 9.00 27.28 12.31 ADDR_CTRL Used with DDR4
DDR0_A12 9.33 29.79 18.92 ADDR_CTRL Used with DDR4
DDR0_A13 23.19 31.52 20.24 ADDR_CTRL Used with DDR4
DDR0_ACT_n 7.98 32.68 17.13 ADDR_CTRL Used with DDR4
DDR0_ALERT_n 17.37 32.54 - N/A Used with DDR4
DDR0_BA0 19.81 26.29 15.83 ADDR_CTRL Used with DDR4
DDR0_BA1 21.85 27.00 17.80 ADDR_CTRL Used with DDR4
DDR0_BG0 15.30 27.61 9.85 ADDR_CTRL Used with DDR4
DDR0_BG1 17.09 26.62 12.79 ADDR_CTRL Used with DDR4
DDR0_CAS_n 11.81 26.42 20.78 ADDR_CTRL Used with DDR4
DDR0_CK0 23.03 34.72 27.15 CK0 Used with LPDDR4 and DDR4
DDR0_CK0_n 21.28 33.13 20.98 CK0 Used with LPDDR4 and DDR4
DDR0_CKE0 20.94 29.26 20.75 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_CKE1 13.68 31.10 - ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_CS0_n 7.80 28.47 16.09 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_CS1_n 18.29 35.18 - ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_DM0 13.95 35.06 31.18 BYTE0 Used with LPDDR4 and DDR4
DDR0_DM1 19.07 28.18 20.84 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ0 16.90 37.82 16.79 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ1 14.21 29.20 20.41 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ2 20.40 31.14 28.20 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ3 17.67 28.54 25.53 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ4 23.82 38.78 18.77 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ5 21.95 32.97 18.96 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ6 24.74 35.55 23.02 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ7 24.31 33.64 21.21 BYTE0 Used with LPDDR4 and DDR4
DDR0_DQ8 23.28 34.75 17.35 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ9 18.16 32.35 18.46 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ10 19.18 32.72 20.21 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ11 17.78 37.01 26.20 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ12 20.45 35.22 16.41 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ13 16.68 32.03 14.95 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ14 24.67 29.99 20.07 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQ15 21.39 26.31 22.73 BYTE1 Used with LPDDR4 and DDR4
DDR0_DQS0 27.23 40.21 23.77 DQS0 Used with LPDDR4 and DDR4
DDR0_DQS0_n 27.39 40.92 24.48 DQS0 Used with LPDDR4 and DDR4
DDR0_DQS1 21.74 39.71 23.32 DQS1 Used with LPDDR4 and DDR4
DDR0_DQS1_n 22.68 41.12 22.39 DQS1 Used with LPDDR4 and DDR4
DDR0_ODT0 29.40 29.31 13.32 ADDR_CTRL Used with DDR4
DDR0_ODT1 18.45 30.02 - ADDR_CTRL Used with DDR4
DDR0_PAR 25.10 28.63 - ADDR_CTRL Used with DDR4
DDR0_RAS_n 10.64 28.63 11.54 ADDR_CTRL Used with DDR4
DDR0_RESET0_n 31.66 32.77 19.01 ADDR_CTRL Used with LPDDR4 and DDR4
DDR0_WE_n 15.43 31.72 18.49 ADDR_CTRL Used with DDR4