SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
When the boot mode configuration are being driven by external inputs, the boot mode configuration inputs are recommended to be stable during the processor POR (cold reset).
When using Ethernet Boot and RGMII, the design must implement a EPHY that enables RGMII_ID mode on the EPHY RX data path and disables RGMII_ID mode on the TX data path by default (the processor implements RGMII_ID on the TX output). The processor ROM is EPHY agnostic and will not programmatically enable/disable RGMII_ID mode on attached EPHYs. Typically, this is accomplished via pin strapping on the EPHY.
Select a EPHY with capability to set the RGMII internal TX delay through pin strap, see the device-specific SK. For more information, see the advisory i2329 MDIO: MDIO interface corruption (CPSW and PRU-ICSS) of the device-specific silicon errata.