SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
The processor includes nine Dual-voltage IO domains (VDDSHVx [x = 0..6], VDDSHV_CANUART and VDDSHV_MCU), where each domain provides power supply to a fixed set of IOs. Each IO domain can be configured for 3.3 V or 1.8 V independently, which determines a common operating voltage for the entire set of IOs powered by the respective IO domain power supply.
Processor pads (pins) designated as CAP_VDDSx [x=0..6], CAP_VDDS_CANUART and CAP_VDDS_MCU are provided for connecting an external capacitor to the internal LDO. A 1-μF (to be connected between these pins and VSS, see the device-specific data sheet,) capacitor is recommended. Refer device-specific data sheet for the recommended capacitor voltage rating.
The capacitors are expected to be placed on the back side of the PCB in the array of the BGA to meet the loop inductance requirements. Choice of capacitor voltage rating could influence the capacitor package (size) selection.
Select a capacitor with ESR < 1 Ω. Ensure board trace connection loop inductance is < 2.5-nH.
The capacitor value recommended does not include variations in value considering DC bias and degradation over time. The capacitor value is independent of IO count and activity. It is required for stability of the LDO to generate BIAS supply. Any value beyond the recommended value could result in over voltage stress.