SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
It is recommended to implement the device reset using a dual input AND gate logic. One of the AND gate input is connected to the processor general purpose input/output (GPIO) pin. The AND gate input has provision for pullup and 0 Ω to isolate the GPIO for testing or debug. The other AND gate input is the Main Domain warm reset status output (RESETSTATz) signal.
In case an ANDing logic is not used and the processor Main Domain warm reset status output (RESETSTATz) is used to reset the attached device, ensure the IO voltage level of the attached device matches the RESETSTATz IO voltage level. A level translator is recommended to match the IO voltage level.