When a single memory (DDR4) device (1
X 16-bit) is used, Point-to-Point topology could be considered.
Summary of point-to-point topology
implementation:
- External terminations (VTT) for address and control signals are not
required.
- For differential clock
(DDR0_CK0, DDR0_CK0_n), AC (differential) termination (2 X R in series
(value = Zo - Single-ended impedance) and a filter capacitor (0.01-μF or
value recommended by the memory manufacturer) connected to the center of two
resistors and VDDS_DDR (DDR PHY IO supply)) is recommended. For Single-ended
impedance value and DDR4 point-to-point connections, see the AM62x DDR
Board Design and Layout Guidelines and device-specific SK.
- VREFCA (VDDS_DDR/2) is the
reference voltage used for control, command and address inputs to the memory
(DDR4) devices. VREFCA can be derived from VDDS_DDR using a resistor divider
(2 resistors (recommended resistor value is 1 kΩ, 1%) connected to VDDS_DDR
and VSS) with filter capacitor (recommended value is 0.1-μF) connected in
parallel to both the resistors. An additional decoupling capacitor is
connected to the VREFCA pin (close to memory (DDR4) device).
Alternatively, adding VTT terminations
for a single memory (DDR4) device on the address and control signals, and using an
Sink/Source DDR Termination Regulator to generate the VTT supply is an acceptable
approach.
When two memory (DDR4) devices (2 X
8-bit) are used, it is recommended to follow the Fly-by topology.
Summary of Fly-by topology
implementation:
- External terminations (VTT)
for address, control and clock signals are recommended.
- Sink/Source DDR Termination
Regulator is recommended to generate the VTT supply.
- The Sink/Source DDR
Termination Regulator generates the reference voltage VREFCA
(VDDS_DDR/2).
- Add decoupling capacitors for
the reference voltage.