SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
The baseline drive impedance and ODT settings for memory (DDR4 / LPDDR4) derived from the Signal Integrity (SI) simulations performed on the SK.
It is recommended to perform simulation for the custom design as the configuration values could be different.
To get an overview of the basic system-level board extraction, simulation, and analysis methodologies for high speed LPDDR4 interfaces, refer LPDDR4 Board Design Simulations chapter of the AM62Ax / AM62Px LPDDR4 Board Design and Layout Guidelines application note.
The drive strength is adjustable using the DDR Register Configuration Tool on SysConfig.
For more information, see the [FAQ] AM62A7 or AM62A3 Custom board hardware design – Processor DDR Subsystem and Device Register configuration. This is a generic FAQ and can also be used for AM625 / AM623 / AM625-Q1 / AM620-Q1 and AM62P / AM62P-Q1 family of processors.