SPRAD21E May   2023  – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 AM62x Processor Family
      1. 1.1.1 AM625
      2. 1.1.2 AM623
      3. 1.1.3 AM625SIP
      4. 1.1.4 AM625-Q1
      5. 1.1.5 AM620-Q1
    2. 1.2 AM62Ax Processor Family
      1. 1.2.1 AM62A7
      2. 1.2.2 AM62A7-Q1
      3. 1.2.3 AM62A3
      4. 1.2.4 AM62A3-Q1
    3. 1.3 AM62Px Processor Family
      1. 1.3.1 AM62P
      2. 1.3.2 AM62P-Q1
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Available and Applicable Collaterals
      1. 2.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
      2. 2.1.2 AM62A7 / AM62A3
      3. 2.1.3 AM62P / AM62P-Q1
    2. 2.2 Hardware Design Guide
      1. 2.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
      2. 2.2.2 AM62A7 / AM62A3
      3. 2.2.3 AM62P / AM62P-Q1
  6. 3 Processor Selection
    1. 3.1 Data Sheet
    2. 3.2 Peripheral Instance Naming Convention
    3. 3.3 Device Ordering and Quality
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
        1. 4.1.1.1 PMIC (Power Management IC)
          1. 4.1.1.1.1 Additional Reference
        2. 4.1.1.2 Discrete Power
          1. 4.1.1.2.1 DC/DC Converter
          2. 4.1.1.2.2 LDO
      2. 4.1.2 AM62A7 / AM62A3
        1. 4.1.2.1 PMIC
        2. 4.1.2.2 Discrete Power
      3. 4.1.3 AM62P / AM62P-Q1
        1. 4.1.3.1 PMIC
        2. 4.1.3.2 Discrete Power
    2. 4.2 Power Control and Protection
      1. 4.2.1 Load Switch
      2. 4.2.2 eFuse
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (SK - Starter Kit)
    2. 5.2 Device-Specific (Processor-Specific, Processor-Family Specific) SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs - External ESD Protection
        6. 5.2.1.6 Peripheral Clock Output Series Resistors
      2. 5.2.2 Additional Information Regarding Reuse of SK Design
        1. 5.2.2.1 Design Notes Added on the SK Schematics
        2. 5.2.2.2 SK Design Files Reuse
    3. 5.3 Before You Begin The Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pin Attributes (Pinout) Verification
      3. 5.3.3  Device Comparison and IOSET
      4. 5.3.4  Note on PADCONFIG Registers
      5. 5.3.5  Processor IO (Signal) Isolation for Fail-Safe Operation
      6. 5.3.6  Reference to Device-Specific SK
      7. 5.3.7  High-Speed Interface Design Guidelines
      8. 5.3.8  Recommended Current Source or Sink for LVCMOS (GPIO) Outputs
      9. 5.3.9  Connection of Slow Ramp Inputs or Capacitors to LVCMOS IOs (Inputs or Outputs)
      10. 5.3.10 Queries and Clarifications Related to Processor During Custom Board Design
  9. 6 Processor Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supply for Core and Peripherals
          1. 6.1.1.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 6.1.1.1.2 AM62P / AM62P-Q1
          3. 6.1.1.1.3 Additional Information
        2. 6.1.1.2 Supply for IO Groups
          1. 6.1.1.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 6.1.1.2.2 AM62P / AM62P-Q1
          3. 6.1.1.2.3 Additional Information
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
        4. 6.1.1.4 Supply Connection for Partial IO Mode (Low Power) Configuration
          1. 6.1.1.4.1 Partial IO Used
          2. 6.1.1.4.2 Partial IO Not Used
          3. 6.1.1.4.3 Data Sheet Reference for Power Sequence
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
        2. 6.1.2.2 AM62A7 / AM62A3 and AM62P / AM62P-Q1
        3. 6.1.2.3 Additional Information
          1. 6.1.2.3.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 6.1.2.3.2 AM62P / AM62P-Q1
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI/ MCU_OSC0_XO)
          2. 6.1.3.1.2 Low Frequency Oscillator (WKUP_LFOSC0_XI/ WKUP_LFOSC0_XO)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to Main Domain)
          4. 6.1.3.1.4 Additional Information
        2. 6.1.3.2 Clock Outputs
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 External Reset Status Outputs
        3. 6.1.4.3 Additional Information
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Bootmode Selection
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Additional Information
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 Additional Information
  10. 7 Processor Peripherals
    1. 7.1 Supply Connections for IO Groups
      1. 7.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
      2. 7.1.2 AM62P / AM62P-Q1
    2. 7.2 Memory Interface (DDRSS (DDR4 / LPDDR4), MMCSD (eMMC / SD / SDIO), OSPI / QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.1.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
            1. 7.2.1.1.1.1 Interface Configuration
            2. 7.2.1.1.1.2 Routing Topology and Terminations
            3. 7.2.1.1.1.3 Resistors for Control and Calibration
            4. 7.2.1.1.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.1.1.5 Data Bit or Byte Swapping
            6. 7.2.1.1.1.6 VTT Termination Schematics Reference
          2. 7.2.1.1.2 AM625SIP
          3. 7.2.1.1.3 AM62A7 / AM62A3
          4. 7.2.1.1.4 AM62P / AM62P-Q1
        2. 7.2.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.2.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
            1. 7.2.1.2.1.1 Interface Configuration
            2. 7.2.1.2.1.2 Routing Topology and Terminations
            3. 7.2.1.2.1.3 Resistors for Control and Calibration
            4. 7.2.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.1.5 Data Bit or Byte Swapping
          2. 7.2.1.2.2 AM625SIP
          3. 7.2.1.2.3 AM62A7 / AM62A3 and AM62P / AM62P-Q1
            1. 7.2.1.2.3.1 Interface Configuration
            2. 7.2.1.2.3.2 Routing Topology and Terminations
            3. 7.2.1.2.3.3 Resistors for Control and Calibration
            4. 7.2.1.2.3.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.3.5 Data Bit or Byte Swapping
      2. 7.2.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.2.2.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
            1. 7.2.2.1.1.1 IO Power Supply
            2. 7.2.2.1.1.2 eMMC (Attached Device) Reset
            3. 7.2.2.1.1.3 Signals Termination
            4. 7.2.2.1.1.4 Capacitors for the Power Supply Rails
          2. 7.2.2.1.2 AM62P / AM62P-Q1
            1. 7.2.2.1.2.1 MMC0 Used
              1. 7.2.2.1.2.1.1 IO Power Supply
              2. 7.2.2.1.2.1.2 eMMC (Attached Device) Reset
              3. 7.2.2.1.2.1.3 Signals Termination
              4. 7.2.2.1.2.1.4 Capacitors for the Power Supply Rails
            2. 7.2.2.1.2.2 MMC0 Not Used
          3. 7.2.2.1.3 Additional Information on eMMC PHY
        2. 7.2.2.2 MMC0 – SD (Secure Digital) Card Interface
        3. 7.2.2.3 MMC1 / MMC2 – SD (Secure Digital) Card Interface
          1. 7.2.2.3.1 IO Power Supply
          2. 7.2.2.3.2 SD Card Supply Reset and Boot Configuration
          3. 7.2.2.3.3 Signals Termination
          4. 7.2.2.3.4 ESD Protection
          5. 7.2.2.3.5 Capacitors for the Power Supply Rails
        4. 7.2.2.4 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) and Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 IO Power Supply
        2. 7.2.3.2 OSPI / QSPI Reset
        3. 7.2.3.3 Signals Termination
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory (Attached Device) Reset
        4. 7.2.4.4 Signals Termination
          1. 7.2.4.4.1 GPMC NAND
        5. 7.2.4.5 Capacitors for the Power Supply Rails
    3. 7.3 External Communication Interface (Ethernet (CPSW3G), USB2.0, PRUSS, UART and CAN)
      1. 7.3.1 Ethernet Interface Using CPSW3G (Common Platform Ethernet Switch 3-Port Gigabit)
        1. 7.3.1.1 IO Power Supply
        2. 7.3.1.2 Ethernet PHY Reset
        3. 7.3.1.3 Ethernet PHY Pin Strapping
        4. 7.3.1.4 Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.4.1 Crystal
          2. 7.3.1.4.2 Oscillator
          3. 7.3.1.4.3 Processor Clock Output (CLKOUT0)
        5. 7.3.1.5 MAC (Data, Control and Clock) Interface Signals Termination
        6. 7.3.1.6 MAC (Media Access Controller) to MAC Interface
        7. 7.3.1.7 MDIO (Management Data Input/Output) Interface
        8. 7.3.1.8 Ethernet MDI (Medium Dependent Interface) Including Magnetics
        9. 7.3.1.9 Capacitors for the Power Supply Rails
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USBn (0..1) Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role-Device Interface
          4. 7.3.2.1.4 USB Type-C
        2. 7.3.2.2 USBn (0..1) Not Used
        3. 7.3.2.3 Additional Information
      3. 7.3.3 Programmable Real-Time Unit Subsystem (PRUSS)
        1. 7.3.3.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
        2. 7.3.3.2 AM62A7 / AM62A3 and AM62P / AM62P-Q1
      4. 7.3.4 Universal Asynchronous Receiver/Transmitter (UART)
      5. 7.3.5 Controller Area Network (CAN)
    4. 7.4 On-Board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI) and Multichannel Audio Serial Ports (MCASP)
      2. 7.4.2 Inter-Integrated Circuit (I2C)
    5. 7.5 User Interface (CSIRX0, DPI, OLDI, DSI), GPIO and Hardware Diagnostics
      1. 7.5.1 Camera Serial Interface (CSI-Rx (CSI-2 port, CSIRX0 Instance))
        1. 7.5.1.1 CSIRX0 Used
        2. 7.5.1.2 CSIRX0 Not Used
      2. 7.5.2 Display Subsystem
        1. 7.5.2.1 Display Parallel Interface (DPI)
          1. 7.5.2.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 and AM62A7 / AM62A3 and AM62P / AM62P-Q1
            1. 7.5.2.1.1.1 IO Power Supply
            2. 7.5.2.1.1.2 DPI (Attached Device) Reset
            3. 7.5.2.1.1.3 Connection
            4. 7.5.2.1.1.4 Signals Termination
            5. 7.5.2.1.1.5 Capacitors for the Power Supply Rails
          2. 7.5.2.1.2 AM620-Q1
        2. 7.5.2.2 Open LVDS Display Interface (OLDI)
          1. 7.5.2.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 and AM62P / AM62P-Q1
            1. 7.5.2.2.1.1 OLDI0 Used
              1. 7.5.2.2.1.1.1 IO Power Supply
              2. 7.5.2.2.1.1.2 OLDI (Attached Device) Reset
              3. 7.5.2.2.1.1.3 OLDI Interface Compatibility
              4. 7.5.2.2.1.1.4 Capacitors for the Power Supply Rails
            2. 7.5.2.2.1.2 OLDI0 Not Used
            3. 7.5.2.2.1.3 Additional Information
          2. 7.5.2.2.2 AM620-Q1 and AM62A7 / AM62A3
        3. 7.5.2.3 Display Serial Interface (DSI)
          1. 7.5.2.3.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 7.5.2.3.2 AM62P / AM62P-Q1
            1. 7.5.2.3.2.1 DSITX0 Used
            2. 7.5.2.3.2.2 DSITX0 Not Used
      3. 7.5.3 General Purpose Input/Output (GPIO)
        1. 7.5.3.1 CLKOUT Available on GPIO
        2. 7.5.3.2 Connection and External Buffering
        3. 7.5.3.3 Additional Information
      4. 7.5.4 On-board Hardware Diagnostics
        1. 7.5.4.1 Monitoring of On-Board Supply Voltages Using Processor
          1. 7.5.4.1.1 Voltage Monitor Pins Used
          2. 7.5.4.1.2 Voltage Monitor Pins Not Used
        2. 7.5.4.2 Internal Temperature Monitoring
        3. 7.5.4.3 Connection of Error Signal Output (MCU_ERRORn)
        4. 7.5.4.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
    6. 7.6 Verifying Board Level Design Issues
      1. 7.6.1 Processor Pin Configuration Using Pinmux Tool
      2. 7.6.2 Schematics Configurations
      3. 7.6.3 Connecting Supply Rails to Pullups
      4. 7.6.4 Peripheral (Sub System) Clock Outputs
      5. 7.6.5 General Debug
        1. 7.6.5.1 Clock Output for Board Bring-Up, Test or Debug
        2. 7.6.5.2 Additional Information
  11. 8 Layout Notes (Added on the Schematic)
  12. 9 Custom Board Design Simulation
  13. 10Additional References
    1. 10.1 FAQ Covering AM6xx Processor Family
    2. 10.2 FAQs - Processor Product Family Wise
    3. 10.3 Processor Attached Devices
  14. 11Summary
  15. 12References
    1. 12.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
    2. 12.2 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
    3. 12.3 AM62P / AM62P-Q1
    4. 12.4 Common for all Family of Processors
    5. 12.5 Master List of Available FAQs - Processor Family Wise
    6. 12.6 FAQs Including Software Related FAQs
    7. 12.7 FAQs for Attached Devices
  16. 13Terminology
  17. 14Revision History

7.4.2 Inter-Integrated Circuit (I2C)

Verify if the application requires a fully compliant I2C interface. The MCU_I2C0 and WKUP_I2C0 are fail-safe, true open-drain output type buffer and fully compliant to the I2C specifications. These can support 3.4-Mbps I2C operations (when the IO buffers (interface) are operating at 1.8 V).

Note: For I2C interfaces with open-drain output type buffer (MCU_I2C0 and WKUP_I2C0), an external pullup is recommended irrespective of peripheral usage and IO configuration.

Refer the Pin Connectivity Requirements section of the device-specific data sheet. A pullup of 4.7 kΩ or similar is recommended.

When these open-drain output type buffer I2C interfaces are pulled to 3.3 V supply, the inputs have slew rate limit specified. An RC could be used to limit the slew rate. Refer Starter Kit SK-AM62P-LP for implementation.

For more information, refer the Connecting Supply Rails to Pullups section of this checklist document.

In case additional I2C interfaces are required, I2C0..3 interfaces could be used.

I2C0..3 interface uses LVCMOS to emulate an open-drain output type buffer and are not fully compliant with the I2C specification, in particular falling edges are fast (< 2 ns). Any devices connected to these ports must be able to function properly with the faster fall time. These support 100-kHz and 400-kHz operation. Pullup resistors are recommended for these I2C signals. Location of the pullups is not critical but connection is important. It is recommended to connect the pullups with the shortest possible stub.

Series resistor (0 Ω) for the I2C interface signals is good to have. For I2C0..3 interface, series resistors could be used to control the falling edge slew rate. The value depends on the custom board design and could be finalized after testing.

For more information, refer below FAQs:

[FAQ] AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 Custom board hardware design – I2C interface

[FAQ] AM62A7 / AM62A3 Custom board hardware design – I2C interface

[FAQ] AM62P / AM62P-Q1 Custom board hardware design – I2C interface

[FAQ] AM62A7-Q1: Internal pull configuration registers for MCU_I2C0 and WKUP_I2C0

If the plan is to use TI provided software, be sure to connect recommended processor I2C (I2C0 for AM62x - TPS65219) interface to the PMIC, as this is the I2C interface used for PMIC control.

Note: When I2C3 interface is used, refer the I2C3 note (can be multiplexed to more than one pin) in the Timing and Switching Characteristics, Peripherals, I2C section of the device-specific data sheet.
Note:

Refer Exceptions in section Timing and Switching Characteristics, I2C of device-specific data sheet during the custom board design.