SPI slave has to be ready to send/receive data when master starts clock.
But, Master has no way of knowing if slave is ready
Slave has to receive all arbitrary length data that master sends Else,
buffer overflows leading to data loss
Slave has to be ready with data to send to master in next clock cycle
Else, 0s are shifted (corruption if in the middle of valid data flow)
No flow control of any sort whatsoever. Therefore, no way to stop transaction in
the middle for Slave to provision additional resources (buffers to receive
cmd/data to be sent to master) Therefore there may be RX underrun and TX data
loss, if master overwhelms slave.