The SOP boot mode latch timing is referenced in Table 2-3. The parameters to take note of are:

• t_{SOP_Sampled}
• t_{SU_SOP}
• t_{H_SOP}
• t_WARMRSTn

While a requirement is to check as part of power sequencing, this is important to emphasize the criticality of the timing of the SOP boot mode pins latching.

There is an additional way to check the timing of these critical signals. The SOP pins are latched in the internal circuit on the AM26x when the device Power Management Unit (PMU) provides a VDD_OK signal. VDD_OK is generated once all device supplies have ramped up and are stable. The last supply to ramp, and thus trigger VDD_OK is VDDA18, the 1.8V Analog LDO supply. VDDA18 ramps once PORz is released. Therefore, the critical sequence for latching the boot mode pins is:

1. PORz releases, goes high
2. 1.8V Analog LDO (VDDA18) supply ramps
3. VDD_OK signal is triggered
4. SOP pin states are sampled

Although there is no explicit device pin signal available to probe and indicate when the SOP pin states are sampled to latch the AM26x boot mode, the VDDA18 ramp can be monitored to find this point. Once the VDD_OK signal is generated, the AM26x device boots for 2-6ms. The last point of boot is the WARMRSTn signal release, in which the boot mode is latched, SOP pins are not necessary to hold the states, and can now be changed.