SPRADP6A February   2025  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Net Checks
    1. 2.1 Verify Proper AM26x Power Rail Voltage Levels
    2. 2.2 Verify Maximum Current Loading
    3. 2.3 AM26x Power Sequencing
    4. 2.4 AM26x Power Topology References
  6. 3Device Boot Status
    1. 3.1 AM26x SOP Pin Status
    2. 3.2 SOP Boot Mode Latch Timing
    3. 3.3 AM26x SOP Pin Isolation
  7. 4Verify UART Output
    1. 4.1 Configure AM26x for UART Boot
    2. 4.2 Configure Host PC for UART Boot Validation
  8. 5Verify JTAG Connection
    1. 5.1 Configure AM26x for JTAG
    2. 5.2 Configure Host PC for JTAG Debug
    3. 5.3 Test the JTAG Connection
    4. 5.4 Connect to the AM26x R5F Core
  9. 6Loading and Executing a Code Example
    1. 6.1 Importing, Building, and Loading the Project
  10. 7Summary
  11. 8References
  12. 9Revision History

3.3 AM26x SOP Pin Isolation

The AM26x SOP signals are on-device pins shared with other digital I/O. Due to the SOP and functional mode multiplexing, additional care needs to be taken in the design phase to make sure that the SOP mode selection resistors, jumpers or switch paths are routed in such a way that the SOP mode branches do not present inductive stubs to the functional mode signal paths. Issues regarding SOP latch timing, functional mode signal integrity or timing issues, especially non-functional OSPI, QSPI or SPI, can be attributed to this, and the PCB layout must be reviewed.

For TI's recommended SOP pin isolation method, reference the SOP Signal Implementation section in the AM26x Hardware Design Guidelines application note.