SPRZ569B November   2024  – September 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   F29H85x, F29P58x, and F29P32x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2. 3.2.1  Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5. 3.2.3  Advisory
      6. 3.2.4  Advisory
      7. 3.2.5  Advisory
      8. 3.2.6  Advisory
      9. 3.2.7  Advisory
      10.      Advisory
      11. 3.2.8  Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.9  Advisory
      16. 3.2.10 Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
      1. 4.1.1 Security: New TI Keys Programmed on Silicon Revision B Devices
    2. 4.2 Silicon Revision A Advisories
      1. 4.2.1 Advisory
      2. 4.2.2 Advisory
      3. 4.2.3 Advisory
      4. 4.2.4 Advisory
      5. 4.2.5 Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1. 5.2.1 Advisory
      2. 5.2.2 Advisory
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

4.2.1 Advisory

Flash: Stand-alone CPU1/CPU3 Reset With Flash Prefetch Enabled may Cause NMI to CPU1/CPU3

Revisions Affected

0, A

Details

If Flash prefetch is enabled, a stand-alone reset issued to CPU1 or CPU3 (for example, debug reset from CCS) may cause an NMI to the CPU because of an uncorrectable ECC error. Below are the sources for a stand-alone CPU reset.

CPU1:

  1. Debug reset
  2. HSM → CPU1.RSn

CPU3:

  1. Debug reset
  2. HSM → CPU3.RSn
  3. CPU3 WD Reset
  4. CPU3 NMIWD Reset
  5. SSU_CPU3_CFG_REGS → CPU_RST_CTRL.SW_SYSRSN

Workaround

Disable Flash prefetch (FRIx_INTF_CTRL.PREFETCH_EN = 0) before issuing a stand-alone reset to the CPU.

CPU1 → FRI1_INTF_CTRL.PREFETCH_EN = 0

CPU3 → FRI3_INTF_CTRL.PREFETCH_EN = 0

FRIx_INTF_CTRL.PREFETCH_EN is writable from CPU1.LINK2 and CPU1/3 debugger if ZONE1 is enabled.