SPRZ569B November   2024  – September 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   F29H85x, F29P58x, and F29P32x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2. 3.2.1  Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5. 3.2.3  Advisory
      6. 3.2.4  Advisory
      7. 3.2.5  Advisory
      8. 3.2.6  Advisory
      9. 3.2.7  Advisory
      10.      Advisory
      11. 3.2.8  Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.9  Advisory
      16. 3.2.10 Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
      1. 4.1.1 Security: New TI Keys Programmed on Silicon Revision B Devices
    2. 4.2 Silicon Revision A Advisories
      1. 4.2.1 Advisory
      2. 4.2.2 Advisory
      3. 4.2.3 Advisory
      4. 4.2.4 Advisory
      5. 4.2.5 Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1. 5.2.1 Advisory
      2. 5.2.2 Advisory
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

1.2 Advisories Matrix

Table 1-2 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
0 A B
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes Yes
MCAN Message Order Inversion When Transmitting From Dedicated Tx Buffers Configured With Same Message ID Yes Yes Yes
ePWM ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window Yes Yes Yes
ePWM ePWM: ePWM TZFRC and TZCLR Events may be Missed When PERCLKDIVSEL.EPWMCLKDIV = 1 Yes Yes Yes
ePWM ePWM: ESM Source for Trip Zone is not Supported Yes Yes Yes
ePWM ePWM: ePWM One-Shot/CBC Trip Event DCxEVTy.force Does Not Set the Trip Condition Yes Yes Yes
ePWM ePWM: For ePWMs Using Global Load in One-Shot Load Mode, Global Load of Registers may get Delayed When a Write to the GLDCTL2.OSHTLD Register Occurs Within 3 TBCLKs of the Global Load Event Yes Yes Yes
Flash Flash: Stand-alone CPU1/CPU3 Reset With Flash Prefetch Enabled may Cause NMI to CPU1/CPU3 Yes Yes No
FOTA FOTA: Secure FOTA With Encryption does not Work Yes Yes No
HRPWM HRPWM: HRPWM High-Resolution Period Shadow to Active Loading Occurs Every ZERO Event, Even if Shadow to Active Load for Period is Set to Only Load on SYNC Yes Yes Yes
HSM HSM: HSM ROM Code Does Not Boot HSMRT Image of Size Greater Than 191KB Yes Yes No
LIN LIN: LIN Unable to Wake Up Using 0xF0 Wake-Up Key Yes Yes Yes
MCD MCD: Missing Clock Detect Should be Disabled When the PLL is Enabled (PLLCLKEN = 1) Yes Yes Yes
MEMSS MEMSS: Data Line Buffer (DLB) for RAM Causes Data Coherency Issue Yes Yes Yes
ROM ROM: By Default, GPIO4 is Configured as ERRORSTS by ROM Code and Driven High Yes No No
SDFM SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger Spurious Comparator Events Yes Yes Yes
SDFM SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious Data Acknowledge Events Yes Yes Yes
SDFM SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events Yes Yes Yes
C29 CPU Subsystem C29 CPU Subsystem: DTHE Interrupts and DMA Events Not Triggered in C29 CPU Subsystem for HS-FS Devices Yes Yes No
System System: Device Reset Remains Asserted When VDD Voltage Ramps Before VDDIO Yes Yes Yes
System System: Pending Misaligned Reads in the Pipeline After CPU Goes to Fault State Preventing NMI Vector Fetch Yes Yes No
UART UART: UART FIFO Gets Cleared on Continuous Debugger Reads Yes Yes Yes
VSSOSC VSSOSC: Coupling From Adjacent Pins X1 or X2 may Prevent Proper Boot Yes No No