SPRZ569B November   2024  – September 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   F29H85x, F29P58x, and F29P32x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2. 3.2.1  Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5. 3.2.3  Advisory
      6. 3.2.4  Advisory
      7. 3.2.5  Advisory
      8. 3.2.6  Advisory
      9. 3.2.7  Advisory
      10.      Advisory
      11. 3.2.8  Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.9  Advisory
      16. 3.2.10 Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
      1. 4.1.1 Security: New TI Keys Programmed on Silicon Revision B Devices
    2. 4.2 Silicon Revision A Advisories
      1. 4.2.1 Advisory
      2. 4.2.2 Advisory
      3. 4.2.3 Advisory
      4. 4.2.4 Advisory
      5. 4.2.5 Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1. 5.2.1 Advisory
      2. 5.2.2 Advisory
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

3.2.5 Advisory

ePWM: For ePWMs Using Global Load in One-Shot Load Mode, Global Load of Registers may get Delayed When a Write to the GLDCTL2.OSHTLD Register Occurs Within 3 TBCLKs of the Global Load Event

Revisions Affected

0, A, B

Details

When a write to the GLDCTL2.OSHTLD register bit occurs within 3 TBCLKs of the global load event (configured by GLDCTL.GLDMODE), the global load of registers (configured by GLDCFG) may get delayed, which can create unintended waveforms.

Workaround

To avoid this issue, any writes to the GLDCTL2.OSHTLD register bit needs to be a minimum of 3 TBCLK cycles before the configured global load event.

Workaround 1 (Recommended): Synchronous ISR to PWMs

  1. Generate an ISR on a known Event Trigger Interrupt event (that is, CMPC, CMPD event, and so forth).
  2. Ensure a minimum of 3 TBCTR cycles are kept between the global load event and when the ISR writes to GLDCTL2.OSHTLD.
    1. When writing to the OSHTLD bit, ensure this is non-interruptible code by disabling the interrupts.
F29H859TU-Q1 F29H850TU Example of Synchronous ISR Loading Method Figure 3-3 Example of Synchronous ISR Loading Method

Workaround 2: Asynchronous updates to PWM registers

  1. Read from the TBCTR of the PWM instance that is enabled for global loading before writing to the GLDCTL2.OSHTLD register.
  2. Ensure at least 3 cycles are kept between the global load event and writes to GLDCTL2.OSHTLD.
    1. Ensure the code reading from TBCTR and writing to the OSHTLD bit is non-interruptible code by disabling interrupts.