SPRZ569B November   2024  – September 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   F29H85x, F29P58x, and F29P32x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2. 3.2.1  Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5. 3.2.3  Advisory
      6. 3.2.4  Advisory
      7. 3.2.5  Advisory
      8. 3.2.6  Advisory
      9. 3.2.7  Advisory
      10.      Advisory
      11. 3.2.8  Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.9  Advisory
      16. 3.2.10 Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
      1. 4.1.1 Security: New TI Keys Programmed on Silicon Revision B Devices
    2. 4.2 Silicon Revision A Advisories
      1. 4.2.1 Advisory
      2. 4.2.2 Advisory
      3. 4.2.3 Advisory
      4. 4.2.4 Advisory
      5. 4.2.5 Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1. 5.2.1 Advisory
      2. 5.2.2 Advisory
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

5.2.1 Advisory

ROM: By Default, GPIO4 is Configured as ERRORSTS by ROM Code and Driven High

Revisions Affected

0

Details

The ROM code configures a GPIO pin for the ERRORSTS function after the device reset (XRSn) based on SECCFG field settings. By default, the ROM code configures the GPIO4 pin as the ERRORSTS pin. The ERRORSTS (GPIO4) pin will be controlled by the Error Signaling Module (ESM) and will be driven high by default (no error). This high state can cause a board issue if the GPIO4 pin is used to drive critical system functions. For example, if GPIO4 is used for the EPWM3_A function, a high-power FET can be turned on inadvertently and cause damage to the board.

Workaround

  1. Avoid using GPIO4 for critical system functions on the board (for example, driving high-power FETs).
  2. If GPIO4 must be used for critical system functions, choose a different GPIO for ERRORSTS by appropriately configuring the SECCFG field. Refer to the empty_driverlib_project_secure example in SDK to see how to change the ERRORSTS pinmux option.

    Since the ROM code configures the GPIO pin for the ERRORSTS function on device reset (XRSn) only, but the ERRORSTS pinmux configuration gets cleared by a debugger reset as well, the user needs to issue a full device reset (XRSn) to rerun the ROM code configuration of ERRORSTS.