SWRS318A November   2024  – June 2025 AWR2944P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram - AWR2944P/AWR2944-ECO/AWR2944LC
    2. 6.2 Pin Diagram - AWR2E44P/AWR2E44-ECO/AWR2E44LC
    3. 6.3 Pin Attributes
    4. 6.4 Signal Descriptions - Digital
    5. 6.5 Signal Descriptions- Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1  QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-64 #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-65
      2. 7.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-236 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-237 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-244 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-245 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-70 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-71 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-73
      3. 7.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1 RGMII/RMII/MII Timing Conditions
          1. 7.12.3.1.1  RGMII Transmit Clock Switching Characteristics
          2. 7.12.3.1.2  RGMII Transmit Data and Control Switching Characteristics
          3. 7.12.3.1.3  RGMII Receive Clock Timing Requirements
          4. 7.12.3.1.4  RGMII Receive Data and Control Timing Requirements
          5. 7.12.3.1.5  RMII Transmit Clock Switching Characteristics
          6. 7.12.3.1.6  RMII Transmit Data and Control Switching Characteristics
          7. 7.12.3.1.7  RMII Receive Clock Timing Requirements
          8. 7.12.3.1.8  RMII Receive Data and Control Timing Requirements
          9. 7.12.3.1.9  MII Transmit Switching Characteristics
          10. 7.12.3.1.10 MII Receive Timing Requirements
          11. 7.12.3.1.11 MII Transmit Clock Timing Requirements
          12. 7.12.3.1.12 MII Receive Clock Timing Requirements
          13. 7.12.3.1.13 MDIO Interface Timings
      4. 7.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5  UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-70BFADF8-F963-4E61-84ED-23FDE518F1A0/T4362547-185
      7. 7.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 7.12.8  CSI2 Receiver Peripheral
        1. 7.12.8.1 CSI2 Switching Characteristics
      9. 7.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 7.12.10 General-Purpose Input/Output
        1. 7.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-45 #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
        4. 8.3.1.4 Processor Subsystem
      2. 8.3.2 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short, Medium, and Long Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.3 Pin Attributes

BALL NUMBER 1PAD NAME 8BALL NAME 2SIGNAL NAME 3MODE 48TYPE 5BALL RESET STATE 6PULL UP/DOWN TYPE 7
AWR2944P/AWR2944-ECO/AWR2944LCAWR2E44P/AWR2E44-ECO/AWR2E44LC

V16

T16PAD_AAMSS_MIBSPIB_CS1MSS_GPIO_120IOOutput DisabledPull Down
MSS_MIBSPIA_HOSTIRQ1O
ADC_VALID2O
MSS_MIBSPIB_CS16IO

B15

C17

PAD_ABMSS_EPWMB0MSS_GPIO_130IOOutput DisabledPull Down
MSS_GPIO_01IO
PMIC_CLKOUT2O
MSS_EPWM_TZ23I
MSS_EPWMA110O
MSS_EPWMB011O

A16

A10PAD_ACMSS_GPIO_1MSS_GPIO_160IOOutput DisabledPull Down
MSS_GPIO_11IO
SYNC_OUT2O
MSS_EPWM_TZ13I
BSS_UARTA_TX7O
READY_INT8O
LVDS_VALID9O
DMM_MUX_IN12I
MSS_MIBSPIB_CS113IO
MSS_MIBSPIB_CS214IO
MSS_EPWMA_SYNCI15I

V12

T13PAD_AHMSS_MIBSPIB_MOSIMSS_GPIO_210IOOutput DisabledPull Up
MSS_MIBSPIB_MOSI1IO
MSS_I2C_SDA2IO
MSS_EPWMA03O
MSS_MCANB_RX7I

U13

T15PAD_AIMSS_MIBSPIB_MISOMSS_GPIO_220IOOutput DisabledPull Up
MSS_MIBSPIB_MISO1IO
MSS_I2C_SCL2IO
MSS_EPWMB03O
DSS_UARTA_TX6IO
MSS_MCANB_TX7O

T13

T14PAD_AJMSS_MIBSPIB_CLKMSS_GPIO_50IOOutput DisabledPull Up
MSS_MIBSPIB_CLK1IO
MSS_UARTA_RX2IO
MSS_EPWMC03O
MSS_UARTB_TX6IO
BSS_UARTA_TX7O
MSS_MCANA_RX8I

U14

U15PAD_AKMSS_MIBSPIB_CS0MSS_GPIO_40IOOutput DisabledPull Up
MSS_MIBSPIB_CS01IO
MSS_UARTA_TX2IO
MSS_UARTB_TX6IO
BSS_UARTA_TX7O
MSS_MCANA_TX9O

U11

P2PAD_ALMSS_QSPI_0MSS_GPIO_80IOOutput DisabledPull Down
MSS_QSPI_01IO
MSS_MIBSPIB_MISO2IO

V11

N2PAD_AMMSS_QSPI_1MSS_GPIO_90IOOutput DisabledPull Down
MSS_QSPI_11I
MSS_MIBSPIB_MOSI2IO
MSS_MIBSPIB_CS28IO

T11

P1PAD_ANMSS_QSPI_2MSS_GPIO_100IOOutput DisabledPull Up
MSS_QSPI_21I
ADC_VALID2O
MSS_MCANA_TX8O

R12

R1PAD_AOMSS_QSPI_3MSS_GPIO_110IOOutput DisabledPull Up
MSS_QSPI_31I
ADC_VALID2O
MSS_MCANA_RX8I

R10

R2PAD_APMSS_QSPI_CLKMSS_GPIO_70IOOutput DisabledPull Down
MSS_QSPI_CLK1IO
MSS_MIBSPIB_CLK2IO
DSS_UARTA_TX6IO

U12

T1PAD_AQMSS_QSPI_CSMSS_GPIO_60IOOutput DisabledPull Up
MSS_QSPI_CS1O
MSS_MIBSPIB_CS02IO
B12A6PAD_ASWARM_RESETWARM_RESET0IOHiZ Input (Open drain)

C11

B6PAD_ATNERROR_OUTNERROR_OUT0OHiZ (Open drain)

C12

B8PAD_AUTCKMSS_GPIO_170IOOutput DisabledPull Down
TCK1I
MSS_UARTB_TX2IO
BSS_UARTA_RX6I
MSS_MCANA_TX8O

C14

B10PAD_AVTMSMSS_GPIO_180IOOutput DisabledPull Up
TMS1IO
BSS_UARTA_TX2O
MSS_MCANA_RX6I

D13

B9PAD_AWTDIMSS_GPIO_230IOOutput DisabledPull Up
TDI1I
MSS_UARTA_RX2IO
DSS_UARTA_RX7IO

D15

B11PAD_AXTDOSOP[0]During Power-upIOutput Enabled
MSS_GPIO_240IO
TDO1O
MSS_UARTA_TX2IO
MSS_UARTB_TX6IO
BSS_UARTA_TX7O
NDMM_EN9O

R15

R19PAD_AYMCU_CLKOUTMSS_GPIO_250IOOutput DisabledPull Down
MCU_CLKOUT1O
TRACE_CLK2O
FRAME_START7O
READY_INT8O
LVDS_VALID9O
BSS_UARTA_RX10I
MSS_EPWMA012O
DMM_CLK14I
OBS_CLKOUT15O

G15

C20PAD_AZMSS_GPIO_2MSS_GPIO_260IOOutput DisabledPull Down
MSS_GPIO_21IO
MSS_UARTB_TX7IO
MSS_GPIO_2IO
SYNC_OUT9O
PMIC_CLKOUT10O
CHIRP_START11O
CHIRP_END12O
FRAME_START13O
MSS_EPWM_TZ014I
LVDS_VALID15O

T17

N19PAD_BAPMIC_CLKOUTSOP[2]During Power-upIOutput DisabledNo Pull
MSS_GPIO_270IO
PMIC_CLKOUT1O
OBS_CLKOUT2O
TRACE_CTL3O
CHIRP_START6O
CHIRP_END7O
FRAME_START8O
READY_INT9O
LVDS_VALID10O
MSS_EPWMA111O
MSS_EPWMB012O
DMM_SYNC13I

R17

P19PAD_BBMSS_GPIO_28MSS_GPIO_280IOOutput DisabledPull Down
SYNC_IN1I
ADC_VALID2O
MSS_UARTB_RX6IO
DMM_MUX_IN7I
DSS_UARTA_RX8IO
SYNC_OUT9O

R14

T17

PAD_BC

MSS_GPIO_29

SOP[1]

During Power-up

I

Output Disabled

Pull Up

MSS_GPIO_29

0

IO

SYNC_OUT

1

O

RCOSC_CLK

2

O

READY_INT

6

O

LVDS_VALID

7

O

DMM_MUX_IN

9

I

MSS_MIBSPIB_CS1

10

IO

MSS_MIBSPIB_CS2

11

IO

MSS_EPWMB0

12

O

MSS_EPWMB1

13

O

F16

B19PAD_BDMSS_RS232_RXMSS_GPIO_150IOOutput DisabledPull Up
MSS_RS232_RX1IO
MSS_UARTA_RX2IO
TRACE_CLK3O
BSS_UARTA_TX6O
MSS_UARTB_RX7IO
MSS_MCANA_RX8I
MSS_I2C_SCL9IO
MSS_EPWMB010O
MSS_EPWMB111O
MSS_EPWMC012O

E17

A19PAD_BEMSS_RS232_TXMSS_GPIO_140IOOutput EnabledPull Up
MSS_RS232_TX1IO
TRACE_CTL2O
MSS_UARTA_TX5IO
MSS_UARTB_TX6IO
BSS_UARTA_TX7O
READY_INT8O
LVDS_VALID9O
MSS_MCANA_TX10O
MSS_I2C_SDA11IO
MSS_EPWMA012O
MSS_EPWMA113O
NDMM_EN14O
MSS_EPWMB015O

U17

T19

PAD_BF

MSS_I2C_SDA

TRACE_DATA_0

0

O

Output Disabled

Pull Down

MSS_GPIO_31

1

IO

DMM0

2

I

MSS_UARTA_TX

4

IO

MSS_GPIO_31

6

IO

MSS_I2C_SDA

10

IO

P17

P20

PAD_BG

MSS_I2C_SCL

TRACE_DATA_1

0

O

Output Disabled

Pull Down

MSS_GPIO_30

1

IO

DMM1

2

I

MSS_EPWMC_SYNCI

3

I

MSS_UARTA_RX

4

IO

MSS_GPIO_0

6

IO

MSS_I2C_SCL

10

IO

T18

M20PAD_BHMSS_GPIO_8TRACE_DATA_20OOutput DisabledPull Down
MSS_GPIO_291IO
DMM22I
MSS_EPWMB_SYNCI3I
MSS_GPIO_16IO
MSS_GPIO_87IO

N15

N20PAD_BIMSS_GPIO_9TRACE_DATA_30OOutput DisabledPull Down
MSS_GPIO_281IO
DMM32I
MSS_EPWMC_SYNCO4O
MSS_GPIO_26IO
MSS_GPIO_97IO

P16

L19PAD_BJMSS_GPIO_3TRACE_DATA_40OOutput DisabledPull Down
MSS_GPIO_31IO
DMM42I
MSS_EPWMB_SYNCO4O
MSS_GPIO_276IO

L15

M19PAD_BKMSS_GPIO_4TRACE_DATA_50OOutput DisabledPull Down
MSS_GPIO_41IO
DMM52I
MSS_EPWM_TZ24I
MSS_UARTB_TX5IO
MSS_GPIO_266IO

M16

J19

PAD_BL

BSS_UARTA_TX

TRACE_DATA_6

0

O

Output Disabled

Pull Down

MSS_GPIO_5

1

IO

DMM6

2

I

MSS_EPWM_TZ1

4

I

BSS_UARTA_TX

5

IO

MSS_GPIO_25

6

IO

MSS_GPIO_10

7

IO

J15

K19PAD_BMMSS_GPIO_11TRACE_DATA_70OOutput DisabledPull Down
MSS_GPIO_61IO
DMM72I
MSS_EPWM_TZ04I
DSS_UARTA_TX5IO
MSS_GPIO_246IO
MSS_GPIO_117IO

D17

C18PAD_BNMSS_MCANA_TXTRACE_DATA_80OOutput DisabledPull Down
MSS_GPIO_71IO
DMM82I
MSS_MCANA_TX4O
MSS_EPWMA_SYNCI5I
MSS_GPIO_236IO

D16

B18PAD_BOMSS_MCANA_RXTRACE_DATA_90OOutput DisabledPull Down
MSS_GPIO_81IO
DMM92I
MSS_MCANA_RX4I
MSS_EPWMA_SYNCO5O
MSS_GPIO_226IO

E15

A18PAD_BPMSS_EPWMA0TRACE_DATA_100OOutput DisabledPull Down
MSS_GPIO_91IO
DMM102I
MSS_EPWMA03O
MSS_EPWMC04O
MSS_GPIO_216IO

C18

—

PAD_BQ

MSS_EPWMA1TRACE_DATA_11

0

O

Output Disabled

Pull Down
MSS_GPIO_10

1

IO

DMM11

2

I

MSS_EPWMA1

3

O

MSS_EPWMC1

4

O

MSS_GPIO_20

6

IO—

B17

A15PAD_BRMSS_MCANB_TXTRACE_DATA_120OOutput DisabledPull Down
MSS_GPIO_111IO
DMM122I
MSS_EPWMB03O
MSS_EPWMA04O
MSS_MCANB_TX5O
MSS_GPIO_196IO

A17

A17PAD_BSMSS_MCANB_RXTRACE_DATA_130OOutput DisabledPull Down
MSS_GPIO_121IO
DMM132I
MSS_EPWMB13O
MSS_EPWMA14O
MSS_MCANB_RX5I
MSS_GPIO_186IO

C17

—PAD_BTMSS_EPWMB0TRACE_DATA_14

0

O

Output DisabledPull Down
MSS_GPIO_13

1

IO

DMM14

2

I

MSS_EPWMC0

3

O

MSS_EPWMB0

4

O

MSS_GPIO_17

6

IO

U8

—PAD_BXMSS_GPIO_17MSS_GPIO_17

0

IO

Output DisabledPull Down
MSS_MII_COL

1

I

MSS_RMII_REFCLK

2

IO

MSS_EPWMA1

6

O

R8

—PAD_BYMSS_I2CA_SDAMSS_GPIO_18

0

IO

Output DisabledHiZ (Open drain)
MSS_MII_CRS

1

I

MSS_RMII_CRS_DV

2

I

MSS_I2CA_SDA

3

IO

MSS_EPWMB1

6

O

U9

U3PAD_BZMSS_I2CA_SCL

MSS_GPIO_19

0IOOutput DisabledHiZ (Open drain)
MSS_RMII_RXER2I
MSS_I2C_SCL3IO
MSS_EPWMC16O

R6

U9PAD_CAMSS_RGMII_TCTLMSS_GPIO_200IOOutput DisabledPull Down
MSS_RMII_TXEN2O
MSS_RGMII_TCTL3O
MSS_EPWMA06O

T7

T7PAD_CBMSS_RGMII_RCTLMSS_GPIO_210IOOutput Disabled
MSS_RGMII_RCTL3I
MSS_RMII_CRS_DV4I
MSS_UARTB_RX5IO
MSS_EPWMB06O

U4

T12PAD_CCMSS_RGMII_TD3MSS_GPIO_220IOOutput DisabledPull Down
MSS_RGMII_TD33O
MSS_UARTB_TX5IO
MSS_EPWMC06O

U6

R12PAD_CDMSS_RGMII_TD2MSS_GPIO_230IOOutput DisabledPull Down
MSS_RGMII_TD23O

U5

U10PAD_CEMSS_RGMII_TD1MSS_GPIO_240IOOutput DisabledPull Down
MSS_RMII_TXD12O
MSS_RGMII_TD13O

U7

U7PAD_CFMSS_RGMII_TD0MSS_GPIO_250IOOutput DisabledPull Down
MSS_RMII_TXD02O
MSS_RGMII_TD03O

V3

T6PAD_CGMSS_RGMII_TCLKMSS_GPIO_260IOOutput DisabledPull Down
MSS_RGMII_TCLK3O

T9

T5PAD_CHMSS_RGMII_RCLKMSS_GPIO_270IOOutput DisabledPull Down
MSS_RGMII_RCLK3I
MSS_RMII_REFCLK4IO

U10

U5PAD_CIMSS_RGMII_RD3MSS_GPIO_280IOOutput Disabled
MSS_RGMII_RD33I

V5

T4PAD_CJMSS_RGMII_RD2MSS_GPIO_290IOOutput Disabled
MSS_RGMII_RD23I

V4

U4PAD_CKMSS_RGMII_RD1MSS_GPIO_300IOOutput Disabled
MSS_RMII_RXD12I
MSS_RGMII_RD13I

V6

T3PAD_CLMSS_RGMII_RD0MSS_GPIO_310IOOutput Disabled
MSS_RMII_RXD02I
MSS_RGMII_RD03I

T5

T2PAD_CMMSS_MDIO_DATAMSS_GPIO_300IOOutput DisabledPull Up
MSS_MDIO_DATA1IO

R4

U2PAD_CNMSS_MDIO_CLKMSS_GPIO_310IOOutput DisabledPull Up
MSS_MDIO_CLK1O

U15

U17PAD_COMSS_MIBSPIA_MOSIMSS_GPIO_00IOOutput DisabledPull Up
MSS_MIBSPIA_MOSI5IO

U16

R18PAD_CPMSS_MIBSPIA_MISOMSS_GPIO_10IOOutput DisabledPull Up
MSS_MIBSPIA_MISO5IO

T16

T18PAD_CQMSS_MIBSPIA_CLKMSS_GPIO_20IOOutput DisabledPull Up
MSS_MIBSPIA_CLK5IO

T15

U18PAD_CRMSS_MIBSPIA_CS0MSS_GPIO_30IOOutput DisabledPull Up
MSS_MIBSPIA_CS05IO

V17

—

PAD_CS

MSS_MIBSPIA_HOSTIRQ

MSS_GPIO_4

0

IO

Output Disabled

Pull Down

MSS_GPIO_2

2

IO

MSS_GPIO_8

3

IO

MSS_MIBSPIA_HOSTIRQ

5

O

MSS_MIBSPIB_CS2

6

IO

MSS_GPIO_2

7

IO

MSS_GPIO_8

10

IO

B16

A16PAD_DAMSS_UARTA_RXMSS_GPIO_120IOOutput DisabledPull Up
MSS_CPTS0_TS_SYNC1O
MSS_GPIO_83IO
MSS_UARTB_TX4IO
MSS_UARTA_RX5IO
DSS_UARTA_TX6IO

C16

B17PAD_DBMSS_UARTA_TXSOP[4]During Power-upIOutput Disabled
MSS_GPIO_130IO
MSS_CPTS0_HW2TSPUSH1I
MSS_GPIO_93IO
MSS_UARTB_RX4IO
MSS_UARTA_TX5IO
DSS_UARTA_RX6IO

A15

A9

PAD_DC

MSS_GPIO_14

MSS_GPIO_14

0

IO

Output Disabled

Pull Up

MSS_CPTS0_HW1TSPUSH

1

I

MSS_GPIO_10

3

IO

DSS_UARTA_TX

4

IO

MSS_UARTA_RX

6

IO

B14

A8

PAD_DD

MSS_GPIO_15MSS_GPIO_15

0

IO

Output Disabled

Pull Up

DSS_UARTA_RX

1

IO

MSS_GPIO_11

3

IO

MSS_UARTA_TX

6

IO

A14

B7

PAD_DE

MSS_GPIO_0

SOP[3]

During Power-up

I

Output Disabled

MSS_GPIO_0

0

IO

DSS_UARTA_TX

1

IO

MSS_EPWMB_SYNCI

3

I

MSS_UARTA_TX

5

IO

MSS_UARTB_TX

6

IO

LVDS_VALID

8

O

MSS_GPIO_31

12

IO

B13

A7PAD_DFXREF_CLK0MSS_GPIO_10IOOutput DisabledPull Down
XREF_CLK01I
MSS_GPIO_83IO
MCU_CLKOUT6O
MSS_GPIO_3012IO

D11

—

PAD_DG

XREF_CLK1

MSS_GPIO_2

0

IO

Output DisabledPull Down
XREF_CLK1

1

I

MSS_GPIO_9

3

IO

PMIC_CLKOUT

7

O

MSS_GPIO_29

12

IO

The following list describes the table column headers:

  1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken based on an example implementation).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
  4. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
  5. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
  6. BALL RESET STATE: The state of the terminal at power-on reset
  7. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • Pull Up: Internal pullup
    • Pull Down: Internal pulldown
    • HiZ
  8. Pin Mux Control Value maps to lower 4 bits of register.
  9. There are some PADs that are not mapped to dedicated BGA PINs. These unused PADs need to be disabled in application