SWRS318A November   2024  – June 2025 AWR2944P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram - AWR2944P/AWR2944-ECO/AWR2944LC
    2. 6.2 Pin Diagram - AWR2E44P/AWR2E44-ECO/AWR2E44LC
    3. 6.3 Pin Attributes
    4. 6.4 Signal Descriptions - Digital
    5. 6.5 Signal Descriptions- Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1  QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-64 #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-65
      2. 7.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-236 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-237 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-244 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-245 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-70 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-71 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-73
      3. 7.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1 RGMII/RMII/MII Timing Conditions
          1. 7.12.3.1.1  RGMII Transmit Clock Switching Characteristics
          2. 7.12.3.1.2  RGMII Transmit Data and Control Switching Characteristics
          3. 7.12.3.1.3  RGMII Receive Clock Timing Requirements
          4. 7.12.3.1.4  RGMII Receive Data and Control Timing Requirements
          5. 7.12.3.1.5  RMII Transmit Clock Switching Characteristics
          6. 7.12.3.1.6  RMII Transmit Data and Control Switching Characteristics
          7. 7.12.3.1.7  RMII Receive Clock Timing Requirements
          8. 7.12.3.1.8  RMII Receive Data and Control Timing Requirements
          9. 7.12.3.1.9  MII Transmit Switching Characteristics
          10. 7.12.3.1.10 MII Receive Timing Requirements
          11. 7.12.3.1.11 MII Transmit Clock Timing Requirements
          12. 7.12.3.1.12 MII Receive Clock Timing Requirements
          13. 7.12.3.1.13 MDIO Interface Timings
      4. 7.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5  UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-70BFADF8-F963-4E61-84ED-23FDE518F1A0/T4362547-185
      7. 7.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 7.12.8  CSI2 Receiver Peripheral
        1. 7.12.8.1 CSI2 Switching Characteristics
      9. 7.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 7.12.10 General-Purpose Input/Output
        1. 7.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-45 #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
        4. 8.3.1.4 Processor Subsystem
      2. 8.3.2 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short, Medium, and Long Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.5 Signal Descriptions- Analog

INTERFACESIGNAL NAMEPIN TYPEDESCRIPTIONBALL NO.

AWR2944P/AWR2944-ECO/AWR2944LC

AWR2E44P/AWR2E44-ECO/AWR2E44LC

Transmitters

TX1

O

Single ended transmitter 1 O/P

B3

Waveguide Launches

TX2

O

Single ended transmitter 2 O/P

B5

Waveguide Launches

TX3

O

Single ended transmitter 3 O/P

B7

Waveguide Launches

TX4

O

Single ended transmitter 4 O/P

B9

Waveguide Launches
Receivers

RX1

I

Single ended receiver 1 I/P

M2

Waveguide Launches

RX2

I

Single ended receiver 2 I/P

K2

Waveguide Launches

RX3

I

Single ended receiver 3 I/P

H2

Waveguide Launches

RX4

I

Single ended receiver 4 I/P

F2

Waveguide Launches
ResetNRESETIPower on reset for chip. Active low. The NRESET needs to be pulled low for a minimum of 20 μsec for proper device reset.

H16

C19
Reference OscillatorCLKPIIn XTAL mode: Input for the reference crystal
In External clock mode: Single ended input reference clock port

D1

E2

CLKMIIn XTAL mode: Feedback drive for the reference crystal
In External clock mode: Connect this port to ground

B1

D1

Reference clockOSC_CLKOUTOReference clock output from clocking subsystem after cleanup PLL

A11

B1

OSC_CLK_OUT_ETH

O

Reference clock to eliminate external oscillator for Ethernet PHY

B11

A2

Bandgap voltageVBGAPODevice's Band Gap Reference Output

K4

J1

Power supplyVDDPower1.2V digital power supplyE12,E13,E14,F14,H14,J14,K14,L14,N6,N14,P6,P7,P9,P10,P11,P13,P14

A11,B20,M14,M15,M16,M18,N13,N15,N17,N18,P13,P15,P17,R14,R16,U8

VDD_SRAMPower1.2V power rail for internal SRAM

V7

U11

VNWAPower1.2V power rail for SRAM array back bias

V13

U16

VIOINPowerI/O Supply (3.3V or 1.8V): All CMOS I/Os can operate on this supplyA13,B18,R18,V8,V15A14,J20,T20,U14
VIOIN_18Power1.8V supply for CMOS IOD18,U18,V10A12,L20,U12,U19
VIOIN_18CLKPower1.8V supply for clock module

D9

A4

VIN_18PMPower1.8V supply for PM module

R1

J2
VIOIN_18LVDSPower1.8V supply for LVDS port

K17

F18,F19,F20,G18
VIOIN_18CSIPower1.8V supply for CSI port

K18

—

VPP

Power

Voltage supply for fuse chain

U3

U6

Power supplyVDDA_10RF1Power1V Analog and RF supply,VDDA_10RF1 and VDDA_10RF2 can be shorted on the board

M4

L1

VDDA_10RF2Power1V Analog and RF supply

D6, D7

A5, B5

VDDA_18BBPower1.8V Analog base band power supply

P1

M1

VDDA_18VCOPower1.8V RF VCO supply

E4

H2
VSS(2)GroundDigital groundA12,A18,E11,E18,F8,F9,F10,F11,F12,F13,G7,G8,G9,G10,G11,G12,G13,G14,H7,H8,H9,H10,H11,H12,H13,J7,J8,J9,J10,J11,J12,J13,K7,K8,K9,K10,K11,K12,K13,K16,L7,L8,L9,L10,L11,L12,L13,M7,M8,M9,M10,M11,M12,M13,M14,N7,N8,N9,N10,N11,N12,N13,P8,P12,P18,V2,V9,V14,V18A13,A20,D17,D18,E17,E18,F17,G17,H12,J12,K20,L14,L16,L18,M12,P12,R20,U1,U13,U20
VSSA(3)GroundAnalog groundA1,A2,A4,A6,A8,A10,B2,B4,B6,B8,B10,C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,D2,D3,E1,E2,E3,F3,F6,F7,G1,G2,G3,G6,H3,H6,J1,J2,J3,J6,K3,K6,L1,L2,L3,L6,M3,M6,N1,N2,N3,V1

A1,A2,A3,B2, B3,B4,B12,B13,B14,B15,B16,C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12,C16,D2,D3,D7,D8,D11,D12,D16,E1,E3,E7,E8,E11,E12,E13,E14,E15,E16,F1,F2,F3,F4,F5,F6,F7,F8,F11,F12,F13,F14,F15,F16,G3,G4,G5,G6,G8,G9,G10,G11,G12,G13,G16,H1,H3,H6,H7,H8,H9,H10,H11,H13,H16,J3,J6,J7,J11,J13,J16,K3,K6,K7,K11,K13,K14,K15,K16,L3,L4,L5,L6,L7,L8,L9,L10,L11,M3,M4,M5,M6,M7,M8,M9,M10,M11,N3,N7,N8,N11,P3,P7,P8,P11,R3,R4,R5,R6,R7,R8,R11,T8,T9,T10,T11

Internal LDO output/inputsVOUT_14APLLOInternal LDO output

H4

G2

VOUT_14SYNTHOInternal LDO output

G4

G1

General purpose ADC inputs for external voltage monitoring(1)ADC1IOADC Channel 1

P3

K2

ADC2IOADC Channel 2

P2

K1
ADC3IOADC Channel 3

R3

N1
ADC4IO

ADC Channel 4

R2

—

ADC5IO

ADC Channel 5

T3

M2

ADC6

IO

ADC Channel 6

U2

L2

ADC7

IO

ADC Channel 7

T1

—

ADC8

IO

ADC Channel 8

T2

—

ADC9

IO

ADC Channel 9

U1

—
(1) For details, see Section 8.4.3
(2) Corner BGAs are VSS and redundant, meaning if the BGAs fail the device still functions.
(3) The VSSA BGAs around the launches are not redundant and are required for functionality.