SWRS318A November   2024  – June 2025 AWR2944P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram - AWR2944P/AWR2944-ECO/AWR2944LC
    2. 6.2 Pin Diagram - AWR2E44P/AWR2E44-ECO/AWR2E44LC
    3. 6.3 Pin Attributes
    4. 6.4 Signal Descriptions - Digital
    5. 6.5 Signal Descriptions- Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1  QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-64 #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-65
      2. 7.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-236 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-237 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-244 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-245 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-70 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-71 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-73
      3. 7.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1 RGMII/RMII/MII Timing Conditions
          1. 7.12.3.1.1  RGMII Transmit Clock Switching Characteristics
          2. 7.12.3.1.2  RGMII Transmit Data and Control Switching Characteristics
          3. 7.12.3.1.3  RGMII Receive Clock Timing Requirements
          4. 7.12.3.1.4  RGMII Receive Data and Control Timing Requirements
          5. 7.12.3.1.5  RMII Transmit Clock Switching Characteristics
          6. 7.12.3.1.6  RMII Transmit Data and Control Switching Characteristics
          7. 7.12.3.1.7  RMII Receive Clock Timing Requirements
          8. 7.12.3.1.8  RMII Receive Data and Control Timing Requirements
          9. 7.12.3.1.9  MII Transmit Switching Characteristics
          10. 7.12.3.1.10 MII Receive Timing Requirements
          11. 7.12.3.1.11 MII Transmit Clock Timing Requirements
          12. 7.12.3.1.12 MII Receive Clock Timing Requirements
          13. 7.12.3.1.13 MDIO Interface Timings
      4. 7.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5  UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-70BFADF8-F963-4E61-84ED-23FDE518F1A0/T4362547-185
      7. 7.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 7.12.8  CSI2 Receiver Peripheral
        1. 7.12.8.1 CSI2 Switching Characteristics
      9. 7.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 7.12.10 General-Purpose Input/Output
        1. 7.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-45 #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
        4. 8.3.1.4 Processor Subsystem
      2. 8.3.2 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short, Medium, and Long Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

4 Device Comparison

Table 4-1 Device Features Comparison
FUNCTION

AWR2944P

AWR2E44P

AWR2944-ECO

AWR2E44-ECO

AWR2944LC

AWR2E44LC

AWR2544

AWR2944
Launch on Package (LOP) Antenna

—

Yes

—

Yes

—Yes

Yes

—
Number of receivers

4

4

4

4

4

4

4

4
Number of transmitters

4

4

4

4

4

4

4

4
On-chip memory

4.5MB

4.5MB

4MB

4MB

3MB

3MB

2MB

4MB
Max I/F (Intermediate Frequency) (MHz)

20

20

20

20

20

20

20

15

Max real/complex 2x sampling rate (Msps)

45(1)

45(1)

45(1)

45(1)

45(1)

45(1)

45(1)

37.5

(1)
Safety and Security(2)
Device Security(3)

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes
AEC-Q100 Qualified

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes
Processor
MCU (RxF)

Yes

YesYesYesYesYesYesYes
DSP (C6xx)

Yes(4)

Yes(4)Yes(4)Yes(4)———Yes(4)
Hardware accelerator(6)

HWA2.1(5)

HWA2.1(5)HWA2.1(5)HWA2.1(5)HWA2.1(5)HWA2.1(5)HWA1.5HWA2.1
DSS_M4 for HWA controlYesYesYesYesYesYes——
Hardware Security Module (HSM)(7)(8)

Yes

YesYesYesYesYes

Yes

Yes
Security Accelerators (7)

Yes

YesYesYesYesYes

Yes

Yes
Peripherals
Serial Peripheral Interface (SPI) ports

2

2

2

2

2

2

1

2
Quad Serial Peripheral Interface (QSPI)

Yes

YesYesYesYesYes

Yes

Yes
LVDS/Debug

Yes

YesYesYesYesYes

Yes

Yes
Aurora LVDS

Yes

YesYesYes———Yes
Ethernet Interface

Yes

YesYesYes——YesYes
Reference Clock for Ethernet

Yes

Yes

YesYes——Yes—
Inter-Integrated Circuit (I2C) interface

1

1

1

1

1

1

1

1
CAN FD

2

2

2

2

2

2

—

2
Trace

Yes

YesYesYesYesYes

Yes

Yes
ePWM

Yes

YesYesYesYesYes

Yes

Yes
DMM Interface

Yes

YesYesYesYesYes

—

Yes
GPADCYes(9)Yes(9)Yes(9)Yes(9)Yes(9)Yes(9)Yes(9)Yes(9)
CSI2 TX——————Yes—
CSI2 RXYesYesYesYes———Yes
JTAGYesYesYesYesYesYes

Yes

Yes
Per chirp configurable Tx phase shifterYesYesYesYesYesYes

Yes

Yes
Product status(10)PRODUCT PREVIEW (PP),
ADVANCE INFORMATION (AI),
or PRODUCTION DATA (PD)

PD

PDPDPD

PD

PD

PD

PD
(1) Supports a real only receiver
(2) Developed for Functional Safety applications, the AWR2944P/AWR2E44P/AWR2944-ECO/AWR2E44-ECO/AWR2944LC/AWR2E44LC device is targeted to support hardware integrity up to ASIL-B. For other devices, refer to the respective data sheets.
(3) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type identifier in the Section 3, Device Information table.
(4) The DSP processing core is upgraded from C67x in AWR1843 to C66x.
(5) User programmable using Arm®Cortex-M4.
(6) The hardware accelerator is upgraded to HWA2.1 with additional features as compared to AWR1843.
(7) Only applicable for Secure Part Variant
(8) User Programmable Arm®Cortex-M4
(9) Has a dedicated GPADC for external voltage monitoring
(1) Device supports CSI2 Rx based playback functionality as a dedicated GPADC for external voltage monitoring.
(10) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.