SWRS318A November   2024  – June 2025 AWR2944P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram - AWR2944P/AWR2944-ECO/AWR2944LC
    2. 6.2 Pin Diagram - AWR2E44P/AWR2E44-ECO/AWR2E44LC
    3. 6.3 Pin Attributes
    4. 6.4 Signal Descriptions - Digital
    5. 6.5 Signal Descriptions- Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1  QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-64 #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-65
      2. 7.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-236 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-237 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-244 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-245 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-70 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-71 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-73
      3. 7.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1 RGMII/RMII/MII Timing Conditions
          1. 7.12.3.1.1  RGMII Transmit Clock Switching Characteristics
          2. 7.12.3.1.2  RGMII Transmit Data and Control Switching Characteristics
          3. 7.12.3.1.3  RGMII Receive Clock Timing Requirements
          4. 7.12.3.1.4  RGMII Receive Data and Control Timing Requirements
          5. 7.12.3.1.5  RMII Transmit Clock Switching Characteristics
          6. 7.12.3.1.6  RMII Transmit Data and Control Switching Characteristics
          7. 7.12.3.1.7  RMII Receive Clock Timing Requirements
          8. 7.12.3.1.8  RMII Receive Data and Control Timing Requirements
          9. 7.12.3.1.9  MII Transmit Switching Characteristics
          10. 7.12.3.1.10 MII Receive Timing Requirements
          11. 7.12.3.1.11 MII Transmit Clock Timing Requirements
          12. 7.12.3.1.12 MII Receive Clock Timing Requirements
          13. 7.12.3.1.13 MDIO Interface Timings
      4. 7.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5  UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-70BFADF8-F963-4E61-84ED-23FDE518F1A0/T4362547-185
      7. 7.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 7.12.8  CSI2 Receiver Peripheral
        1. 7.12.8.1 CSI2 Switching Characteristics
      9. 7.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 7.12.10 General-Purpose Input/Output
        1. 7.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-45 #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
        4. 8.3.1.4 Processor Subsystem
      2. 8.3.2 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short, Medium, and Long Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

1 Features

  • FMCW transceiver
    • Integrated PLL, transmitter, receiver, baseband and ADC
    • 76GHz to 81GHz coverage with 5GHz available BW with 4 receive and 4 transmit channels
      • AWR2944P/AWR2944-ECO/AWR2944LC: PCB interface to antennas
      • AWR2E44P/AWR2E44-ECO/AWR2E44LC: Launch-on-Package (LOP) interface to antennas
    • Per transmit phase shifter
    • Ultra-accurate chirp engine via fractional-N PLL
    • TX power
      • AWR2944P: 14dBm

      • AWR2944-ECO/AWR2944LC: 13.5dBm

      • AWR2E44P: 13.5dBm

      • AWR2E44-ECO/AWR2E44LC: 12.5dBm

    • RX noise figure
      • AWR2944P: 10.5dB
      • AWR2944-ECO/AWR2944LC: 12dB
      • AWR2E44P: 11dB
      • AWR2E44-ECO/AWR2E44LC: 12.5dB
    • Phase noise at 1MHz
      • VCO1: -96dBc/Hz (76 to 77GHz)
      • VCO2: -95dBc/Hz (76 to 81GHz)
  • Processing elements
    • Arm®Cortex-R5F® core (supports lock step operation) @400MHz
    • TI digital signal processor C66x @450MHz

      Not applicable to 2944LC and AWR2E44LC

    • TI radar hardware accelerator (HWA2.1) for operations like FFT, log magnitude, and memory compression
    • Multiple EDMA instances for data movement
    • Programmable embedded hardware security module (HSM) using Arm®Cortex-M4
    • Second Arm® Cortex M4 core in the DSS (DSP Subsystem), controlling and configuring the HWA2.1
  • Functional safety compliant targeted
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Hardware integrity up to ASIL B targeted
  • Other interfaces available to user application (on select part numbers)
    • Up to 9 ADC channels based on device variant
    • 2 SPIs | 4 UARTs | I2C | GPIOs | 3 EPWMs
    • 4-lane Aurora LVDS interface for raw ADC data and debug instrumentation
    • 2-lane CSI2 Rx for playback of captured data
  • On-Chip RAM (split between DSP, MCU, and shared L3)
    • 3MB to 4.5MB of ‘On Chip’ RAM (AWR2944P/AWR2E44P: 4.5MB, AWR2944-ECO/AWR2E44-ECO: 4MB, AWR2944LC//AWR2E44LC: 3MB)
  • Host interface
    • 2x CAN-FD
    • 10/100/1000Mbps Ethernet
      • 10/100Mbps for the AWR2944-ECO/AWR2E44-ECO
      • Not applicable to AWR2944LC/AWR2E44LC
  • Supports a serial flash memory interface (loading user application from QSPI flash memory)
  • Device security (on select part numbers)
    • Secure authenticated and encrypted boot support
    • Customer programmable root keys, symmetric keys (256 bit), asymmetric keys (up to RSA-4K or ECC-512) with key revocation capability
    • Cryptographic hardware accelerators: PKA with ECC, AES (up to 256 bit), SHA (up to 512 bit), TRNG/DRBG, and SM2, SM3, SM4 (Chinese crypto algorithms)
  • Built-in firmware (ROM) and Self-calibrating system across process and temperature
  • AEC-Q100 qualified
  • Advanced features
    • Embedded self-monitoring with no external processor involvement
    • Embedded interference detection capability
  • Power management
    • On-die LDO network for enhanced PSRR
    • LVCMOS IO supports dual voltage 3.3V and 1.8V
  • Clock source
    • 50/40MHz crystal with internal oscillator
    • Supports externally driven oscillator or clock (square or sine wave) at 50/40MHz
    • 25MHz external clock to eliminate external crystal oscillator for Ethernet PHY when using the 50MHz clock.
  • Optimal Power Management Solution
    • Recommended LP87745-Q1 Power Management ICs (PMIC)
      • Companion PMIC specially designed to meet device power supply requirements
      • Flexible mapping and factory programmed configurations to support different use cases
  • Cost-reduced hardware design using 0.65mm pitch FCCSP package
    • AWR2944P/AWR2944-ECO/AWR2944LC: 12mm × 12mm
    • AWR2E44P/AWR2E44-ECO/AWR2E44LC: 13.5mm × 12mm
  • Supports automotive junction temperature operating range of –40°C to 140°C