TIDUFA5 December 2024
Layout in SEPIC and Cuk is critical. While designing, the most important rule is to reduce the noise in the high-current switching loop, shown in Figure 5-2. The current flows from the input supply to the primary inductor and through the MOSFET. To minimize induced EMF due to switching currents, it is desirable to keep parasitic inductance of this loop as low as possible. Components (primary inductors, input electrolytic capacitors, and FET) must be placed as close as possible to each other. In this layout, a single ground plane was used, and all the signals return onto this low-impedance plane, as shown in Figure 5-3. In case the high-voltage circuit is placed in proximity to the transducer, shielding can be necessary to minimize the effects of radiated interference from the high-voltage section.
Figure 5-3 High Voltage Layout
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