TIDUFA5 December   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Small Compact Size
      2. 2.2.2 Transformerless Design
    3. 2.3 Highlighted Products
      1. 2.3.1  BQ25790 IIC Controlled, 1–4 Cell, 5A Buck-Boost Battery Charger
      2. 2.3.2  TPS3422 Low-Power, Push-Button Controllers With Configurable Delay
      3. 2.3.3  SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset
      4. 2.3.4  TPS259470 2.7V–23V, 5.5A, 28mΩ True Reverse Current Blocking eFuse
      5. 2.3.5  TPS54218 2.95V to 6V Input, 2A Synchronous Step-Down SWIFT Converter
      6. 2.3.6  TPS54318 2.95V to 6V Input, 3A Synchronous Step-Down SWIFT Converter
      7. 2.3.7  LM5158 2.2MHz, Wide VIN, 85V Output Boost, SEPIC, or Flyback Converter
      8. 2.3.8  TPS61178 20V Fully Integrated Sync Boost With Load Disconnect
      9. 2.3.9  LMZM23601 36V, 1A Step-Down DC-DC Power Module in 3.8mm × 3mm Package
      10. 2.3.10 TPS7A39 Dual, 150mA, Wide-VIN, Positive and Negative Low-Dropout (LDO) Voltage Regulator
      11. 2.3.11 TPS74401 3.0A, Ultra-LDO With Programmable Soft Start
      12. 2.3.12 TPS7A96 2A, Ultra-Low Noise, Ultra-high PSRR RF Voltage Regulator
      13. 2.3.13 LM3880 3-Rail Simple Power Sequencer With Fixed Time Delay
      14. 2.3.14 DAC53401 10-Bit, Voltage-Output DAC With Nonvolatile Memory
      15. 2.3.15 INA231 28V, 16-bit, I2C Output Current, Voltage, and Power Monitor With Alert in WCSP
  9. 3System Design Theory
    1. 3.1 Input Section
      1. 3.1.1 Buck-Boost Charger
      2. 3.1.2 Power On or Off
    2. 3.2 Designing SEPIC and Cuk Based High-Voltage Power Supply
      1. 3.2.1 Basic Operation Principle of SEPIC and Cuk Converters
      2. 3.2.2 Dual High-Voltage Power Supply Design Using Uncoupled Inductors With SEPIC and Cuk
        1. 3.2.2.1 Duty Cycle
        2. 3.2.2.2 Inductor Selection
        3. 3.2.2.3 Power MOSFET Verification
        4. 3.2.2.4 Output Diode Selection
        5. 3.2.2.5 Coupling Capacitor Selection
        6. 3.2.2.6 Output Capacitor Selection
        7. 3.2.2.7 Input Capacitor Selection
        8. 3.2.2.8 Programming the Output Voltage With Adjustable function
    3. 3.3 Designing the Low-Voltage Power Supply
      1. 3.3.1 Designing the TPS54218 Through WEBENCH Power Designer
      2. 3.3.2 ±5V Transmit Supply Generation
    4. 3.4 System Clock Synchronization
    5. 3.5 Power and Data Output Connector
    6. 3.6 System Current and Power Monitoring
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Efficiency Test Result
      2. 4.3.2 Line Regulation Testing Result
      3. 4.3.3 Spectrum Test Result
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 High-Voltage Supply Layout
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks

3.2.1 Basic Operation Principle of SEPIC and Cuk Converters

In a single-ended primary inductance converter (SEPIC) and Cuk design, the output voltage can be higher or lower than the input voltage. Figure 3-3 shows the SEPIC topology using the two inductors: L1, L2 and Figure 3-4 shows the Cuk converter topology using the L3 and L4 inductors. The two inductors can be wound on the same core, or uncoupled since the same voltages are applied to them throughout the switching cycle. Figure 3-3 and Figure 3-4 illustrate that the Cuk topology was obtained by the exchange position of the diode and second inductor with the SEPIC topology.

Note: The output of Cuk is negative or minus but the output of SEPIC is positive.

To understand the voltages of the various circuit nodes for the SEPIC converter, analyze the circuit at DC when Q1 is off and not switching. During steady-state CCM, pulse-width modulation (PWM) operation, and neglecting ripple voltage, capacitor C1 is charged to the input voltage, Vin. When Q1 is off, the voltage across L2 must be Vout. So, the voltage across Q1 when Q1 is switched off is equal to Vin + Vout, then the voltage across L1 is Vout. When Q1 is on, capacitor C1, charged to Vin, is connected in parallel with L2, so the voltage across L2 is –Vin.

Figure 3-3 shows the currents flowing through various circuit components. When Q1 is on, energy is being stored in L1 from the input and in L2 from C1. When Q1 turns off, the L1 current continues to flow through C1 and D1, and into C2 and the load. Both C1 and C2 get recharged to provide the load current and charge L2, respectively, when Q1 turns back on (see Figure 3-3 and Figure 3-5), see the AN-1484 Designing A SEPIC Converter application note.

To understand the voltages of at the various circuit nodes for the Cuk converter, analyze the circuit at DC when Q2 is off and not switching. During steady-state CCM, pulse-width modulation (PWM) operation, and neglecting ripple voltage, capacitor C3 is charged to Vin – Vout. When Q2 is off, the voltage across L4 must be Vout. The voltage across Q1 when Q1 is switched off equals Vin – Vout, then the voltage across L3 is –Vout. When Q2 is on, capacitor C3 is charged to Vin – Vout, thus connected in series with L4, so the voltage across L4 is –Vin. Figure 3-4 shows the currents flowing through various circuit components. When Q2 is on, energy is being stored in L3 from the input and in L4 from C3. When Q2 turns off, the current from L3 continues to flow through C3 and D2, the current of L4 is charged into C4 and the load. Both C3 and C4 get recharged so that these capacitors can provide the load current and charge L4, respectively, when Q1 turns back on. See Figure 3-4 and Figure 3-6 and see TI-Cuk training for more information.

TIDA-010269 SEPIC TopologyFigure 3-3 SEPIC Topology

TIDA-010269 Cuk Converter Topology

Figure 3-4 Cuk Converter Topology
TIDA-010269 Current Loop When the SEPIC MOSFET Switch is OnFigure 3-5 Current Loop When the SEPIC MOSFET Switch is On

TIDA-010269 Current Loop When the Cuk MOSFET Switch is On

Figure 3-6 Current Loop When the Cuk MOSFET Switch is On

TIDA-010269 Current Loop When SEPIC MOSFET Switch is Off

Figure 3-7 Current Loop When SEPIC MOSFET Switch is Off
TIDA-010269 Current Loop When Cuk MOSFET Switch is OffFigure 3-8 Current Loop When Cuk MOSFET Switch is Off

The formulas for the duty cycle between input voltage and output voltage for SEPIC (Equation 2) and Cuk (Equation 3) follow:

Equation 2. D = V o u t p u t + V D V i n + V o u t p u t + V D
Equation 3. D = - V o u t p u t + V D V i n - V o u t p u t + V D

Equation 2 and Equation 3 are exactly same since the output of Cuk is negative. Here Vin is input voltage, VD is forward voltage of diode, Voutput is output voltage. This hints that the output voltage keeps the amplitude the same, and under control if the load is same.

Equation 4 (SEPIC) and Equation 5 (Cuk) show the voltage calculation that MOSFET maximum endures during switching.

Equation 4. V Q 1 = V i n + V o u t p u t + V D + V C 1 _ r i p p l e 2
Equation 5. V Q 2 = V i n - V o u t p u t + V D + V C 3 _ r i p p l e 2

Equation 6 (SEPIC) and Equation 7 (Cuk) show the maximum voltage that the diode endures during switching.

Equation 6. V D 1 = V i n + V o u t p u t + V D + V C 1 _ r i p p l e 2
Equation 7. V D 2 = V i n - V o u t p u t + V D + V C 3 _ r i p p l e 2

Equation 8 (SEPIC) and Equation 9 (Cuk) show the maximum voltage that the couple capacitor can endure during switching.

Equation 8. V C 1 = V i n + V C 1 _ r i p p l e 2
Equation 9. V C 3 = V i n - V o u t p u t + V C 3 _ r i p p l e 2

Figure 3-9 and Figure 3-10 show the typical node waveform for SEPIC and Cuk, respectively.

TIDA-010269 SEPIC Switching WaveformsFigure 3-9 SEPIC Switching Waveforms

TIDA-010269 Cuk Converter Switching Waveforms

Figure 3-10 Cuk Converter Switching Waveforms

In ultrasound smart-probe imaging applications, the transmitter needs an amplitude that equals the positive and negative high-voltage power supply with a small package. As previously-mentioned, the designer can merge SEPIC and Cuk topologies together to meet the smart-probe application requirements. The output of positive and negative has an equal amplitude since the load in the ultrasound application is matched under any conditions, in theory, and the duty-cycle is exactly same for SEPIC and Cuk. So, in this reference design, SEPIC and Cuk topology was merged to generate a high-voltage power supply from a low-input voltage.