TIDUFB3 July   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS7H5006-SEP
      2. 2.3.2 TPS7H6025-SEP
      3. 2.3.3 TPS7H1111-SEP
      4. 2.3.4 TPS7H4010-SEP
      5. 2.3.5 TPS73801-SEP
      6. 2.3.6 TPS7H3302-SEP
      7. 2.3.7 TPS7H3014-SEP
      8. 2.3.8 TPS7H2221-SEP
      9. 2.3.9 SN54SC6T14-SEP
  9. 3System Design Theory
    1. 3.1 0V8 Discrete Buck Regulator (VCCINT)
      1. 3.1.1 VCCINT Load Step
    2. 3.2 Buck Regulators (Integrated)
      1. 3.2.1 1V2
      2. 3.2.2 1V2_VCCO
      3. 3.2.3 1V2_MEM
      4. 3.2.4 2V5_DDR_VPP
      5. 3.2.5 3V3_VCCO
    3. 3.3 Linear Regulators
      1. 3.3.1 DDR Termination
      2. 3.3.2 0V92
      3. 3.3.3 1V5_GTY
      4. 3.3.4 1V5
      5. 3.3.5 5V0_SYS
    4. 3.4 Sequencing
      1. 3.4.1 TPS7H3014-SP Sequencer
      2. 3.4.2 TPS7H2221-SEP Discharge Circuit
      3. 3.4.3 VCCINT Discharge Circuit
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Discrete Buck Regulator (VCCINT)
        1. 4.3.1.1 0V8
      2. 4.3.2 Buck Regulators (Integrated)
        1. 4.3.2.1 1V2
        2. 4.3.2.2 1V2_VCCO
        3. 4.3.2.3 1V2_MEM
        4. 4.3.2.4 2V5_DDR_VPP
        5. 4.3.2.5 3V3_VCCO
      3. 4.3.3 Linear Regulators
        1. 4.3.3.1 0V6_VTT
        2. 4.3.3.2 0V92
        3. 4.3.3.3 1V5_GTY
        4. 4.3.3.4 1V5
        5. 4.3.3.5 5V0_SYS
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 Layout Prints
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  12. 6About the Author

4.3.1.1 0V8

Unless otherwise noted, VIN = 12V in Figure 4-1 to Figure 4-27.

TIDA-050088 Efficiency
Figure 4-1 Efficiency
TIDA-050088 Load Step: 20A to 31A at 56A/µs
VOUT(drop) = 24.8mV, ILOAD_STEP is measured using the voltage across the R38 load step resistor, the measurement does not include the 20A DC current
Figure 4-3 Load Step: 20A to 31A at 56A/µs
TIDA-050088 Load Step: 31A to 20A at 83A/µs
VOUT(rise) = 24.0mV, ILOAD_STEP is measured using the voltage across the R38 load step resistor, the measurement does not include the 20A DC current
Figure 4-5 Load Step: 31A to 20A at 83A/µs
TIDA-050088 Load Step: 20A to 31A to 20A Load Step
Figure 4-7 Load Step: 20A to 31A to 20A Load Step
TIDA-050088 Output Voltage Ripple at 0A
Figure 4-9 Output Voltage Ripple at 0A
TIDA-050088 Switch Node at 0A
VSW(max) = 12.2V
Figure 4-11 Switch Node at 0A
TIDA-050088 Switch Node at 44A
VSW(max) = 11.8V
Figure 4-13 Switch Node at 44A
TIDA-050088 Gate Signals at 2A
HSG is with respect to SW and is calculated with the oscilloscope using GND referenced measurements: VHSG – VSW
Figure 4-15 Gate Signals at 2A
TIDA-050088 Dead time: Low to High
IOUT = 44A
Figure 4-17 Dead time: Low to High
TIDA-050088 Current Sense Signal at 0A
Figure 4-19 Current Sense Signal at 0A
TIDA-050088 Bode Plot at 100mA
Phase Margin = 78°, Gain Margin = 22dB
Figure 4-21 Bode Plot at 100mA
TIDA-050088 Bode Plot at 40A
Phase Margin = 57°, Gain Margin = 16dB
Figure 4-23 Bode Plot at 40A
TIDA-050088 Thermals at 30A
Figure 4-25 Thermals at 30A
TIDA-050088 Thermals at 44A
Figure 4-27 Thermals at 44A
TIDA-050088 Load Regulation
Local ground
Figure 4-2 Load Regulation
TIDA-050088 Load Step: 20A to 31A at 200A/µs
VOUT(drop) = 26.4mV, ILOAD_STEP is measured using the voltage across the R38 load step resistor, the measurement does not include the 20A DC current
Figure 4-4 Load Step: 20A to 31A at 200A/µs
TIDA-050088 Load Step: 31A to 20A at 200A/µs
VOUT(rise) = 28.4mV, ILOAD_STEP is measured using the voltage across the R38 load step resistor, the measurement does not include the 20A DC current
Figure 4-6 Load Step: 31A to 20A at 200A/µs
TIDA-050088 Switch Node and Switching Frequency
fSW = 272kHz, IOUT = 2A
Figure 4-8 Switch Node and Switching Frequency
TIDA-050088 Output Voltage Ripple at 44A
Figure 4-10 Output Voltage Ripple at 44A
TIDA-050088 Switch Node at 2A
VSW(max) = 12.6V
Figure 4-12 Switch Node at 2A
TIDA-050088 Gate Signals at 0A
HSG is with respect to SW and is calculated with the oscilloscope using GND referenced measurements: VHSG – VSW
Figure 4-14 Gate Signals at 0A
TIDA-050088 Gate Signals at 44A
HSG is with respect to SW and is calculated with the oscilloscope using GND referenced measurements: VHSG – VSW
Figure 4-16 Gate Signals at 44A
TIDA-050088 Dead time: High to Low
IOUT = 44A
Figure 4-18 Dead time: High to Low
TIDA-050088 Current Sense Signal at 44A
Figure 4-20 Current Sense Signal at 44A
TIDA-050088 Bode Plot at 10A
Phase Margin = 64°, Gain Margin = 19dB
Figure 4-22 Bode Plot at 10A
TIDA-050088 Bode Plot at 44A
Phase Margin = 60°, Gain Margin = 18dB
Figure 4-24 Bode Plot at 44A
TIDA-050088 Thermals at 40A
Figure 4-26 Thermals at 40A