TIDUFB3 July   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS7H5006-SEP
      2. 2.3.2 TPS7H6025-SEP
      3. 2.3.3 TPS7H1111-SEP
      4. 2.3.4 TPS7H4010-SEP
      5. 2.3.5 TPS73801-SEP
      6. 2.3.6 TPS7H3302-SEP
      7. 2.3.7 TPS7H3014-SEP
      8. 2.3.8 TPS7H2221-SEP
      9. 2.3.9 SN54SC6T14-SEP
  9. 3System Design Theory
    1. 3.1 0V8 Discrete Buck Regulator (VCCINT)
      1. 3.1.1 VCCINT Load Step
    2. 3.2 Buck Regulators (Integrated)
      1. 3.2.1 1V2
      2. 3.2.2 1V2_VCCO
      3. 3.2.3 1V2_MEM
      4. 3.2.4 2V5_DDR_VPP
      5. 3.2.5 3V3_VCCO
    3. 3.3 Linear Regulators
      1. 3.3.1 DDR Termination
      2. 3.3.2 0V92
      3. 3.3.3 1V5_GTY
      4. 3.3.4 1V5
      5. 3.3.5 5V0_SYS
    4. 3.4 Sequencing
      1. 3.4.1 TPS7H3014-SP Sequencer
      2. 3.4.2 TPS7H2221-SEP Discharge Circuit
      3. 3.4.3 VCCINT Discharge Circuit
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Discrete Buck Regulator (VCCINT)
        1. 4.3.1.1 0V8
      2. 4.3.2 Buck Regulators (Integrated)
        1. 4.3.2.1 1V2
        2. 4.3.2.2 1V2_VCCO
        3. 4.3.2.3 1V2_MEM
        4. 4.3.2.4 2V5_DDR_VPP
        5. 4.3.2.5 3V3_VCCO
      3. 4.3.3 Linear Regulators
        1. 4.3.3.1 0V6_VTT
        2. 4.3.3.2 0V92
        3. 4.3.3.3 1V5_GTY
        4. 4.3.3.4 1V5
        5. 4.3.3.5 5V0_SYS
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 Layout Prints
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  12. 6About the Author

1.1 Key System Specifications

The rails in the system, listed in Table 1-1, are all powered from a 12V input called the 12V0_SYS rail.

Table 1-1 Versal™ Edge and DDR4 Specifications
RAIL SEQUENCE RAIL NAME(1) VERSAL EDGE PINS, DDR POWERED RAIL CURRENT DC ACCURACY AC ACCURACY COMBINED ACCURACY(2) LOAD STEP PARTS
0(3) 5V0_SYS – – – – – – TPS73801-SEP
1 3V3_VCCO

HDIO (bank 302)

PSIO (bank 50x)

 4A ±1% –5%, +3% -6%, +4% 4A at 10A/µs TPS7H4010-SEP
2V5_DDR_VPP DDR_VPP 0.1A –5%, +10% – N/A – TPS7H4010-SEP
1V2_MEM DDR_VDDQ 3A ±5% – N/A – TPS7H4010-SEP
1V2_VCCO XPIO (bank 7xx) 2A ±1% ±5% ±6% 2A at 10A/µs TPS7H4010-SEP
VTT (0V6) DDR4_VTT ±3A ±5% – N/A – TPS7H3302-SEP
VTTREF (0V6) DDR4_VTTREF ±10mA ±1% to VTTSNS ±1% N/A –
2 0V80

VCCINT

VCC_IO

VCC_SOC

VCC_RAM

VCC_PMC

VCC_PSLP

 44A ±1% ±17mV ±3.125% 11A at 200A/μs

TPS7H5006-SEP

TPS7H6025-SEP

5xEPC7019G
3 1V5

VCCAUX_SMON

VCCAUX_PMC

 1.5A ±1% ±2% ±3% 900mA at 10A/μs TPS7H1111-SEP
4 0V92 VGTYP_AVCC 1A ±2% ±10mV ±3.09% 195mA at 10A/μs TPS7H1111-SEP
5 1V5_GTY VGTY_AVCCAUX 0.1A ±2% ±10mV ±2.67% TPS7H1111-SEP
6 1V2

VGTY_AVTT

VGTY_AVTTRCAL

 1.3A ±2% ±10mV ±2.83% 330mA at 10A/µs TPS7H4010-SEP
(1) This is the maximum expected current for the FPGA or DDR. See the power tree in Table 2-1 for the designed current which can be greater than this rail current for margin and powering of other loads. As rail requirements can differ by application, consult the AMD Power Design Manager (PDM) and the DDR specifications for additional information.
(2) This is the combined AC and DC accuracy that is targeted for the Versal Edge rails.
(3) This is not part of the sequencing, the rail comes up as soon as 12V0_SYS is applied.