TIDUFB3 July   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS7H5006-SEP
      2. 2.3.2 TPS7H6025-SEP
      3. 2.3.3 TPS7H1111-SEP
      4. 2.3.4 TPS7H4010-SEP
      5. 2.3.5 TPS73801-SEP
      6. 2.3.6 TPS7H3302-SEP
      7. 2.3.7 TPS7H3014-SEP
      8. 2.3.8 TPS7H2221-SEP
      9. 2.3.9 SN54SC6T14-SEP
  9. 3System Design Theory
    1. 3.1 0V8 Discrete Buck Regulator (VCCINT)
      1. 3.1.1 VCCINT Load Step
    2. 3.2 Buck Regulators (Integrated)
      1. 3.2.1 1V2
      2. 3.2.2 1V2_VCCO
      3. 3.2.3 1V2_MEM
      4. 3.2.4 2V5_DDR_VPP
      5. 3.2.5 3V3_VCCO
    3. 3.3 Linear Regulators
      1. 3.3.1 DDR Termination
      2. 3.3.2 0V92
      3. 3.3.3 1V5_GTY
      4. 3.3.4 1V5
      5. 3.3.5 5V0_SYS
    4. 3.4 Sequencing
      1. 3.4.1 TPS7H3014-SP Sequencer
      2. 3.4.2 TPS7H2221-SEP Discharge Circuit
      3. 3.4.3 VCCINT Discharge Circuit
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Discrete Buck Regulator (VCCINT)
        1. 4.3.1.1 0V8
      2. 4.3.2 Buck Regulators (Integrated)
        1. 4.3.2.1 1V2
        2. 4.3.2.2 1V2_VCCO
        3. 4.3.2.3 1V2_MEM
        4. 4.3.2.4 2V5_DDR_VPP
        5. 4.3.2.5 3V3_VCCO
      3. 4.3.3 Linear Regulators
        1. 4.3.3.1 0V6_VTT
        2. 4.3.3.2 0V92
        3. 4.3.3.3 1V5_GTY
        4. 4.3.3.4 1V5
        5. 4.3.3.5 5V0_SYS
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 Layout Prints
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  12. 6About the Author

3.2.5 3V3_VCCO

The TPS7H4010-SEP synchronous buck converter is selected to generate the required 3.3V directly from the 12V rail. The Versal Edge VCCO_HDIO (bank 302) rails are estimated to require 2A, the VCCO_500, VCCO_501, and VCCO_503 (PSIO banks) and VCCO_502 (PSIO bank) are estimated to require 2A, the TPS7H3302-SEP VDD input is estimated to require 30mA, and the TPS7H1111-SEP bias rails are estimated to require 81mA. Therefore, TPS7H4010-SEP is sized for 6A to provide reasonable margin.

A switching frequency of 1MHz and a 1.8μH XAL6030-182ME_ inductor is selected to provide a reasonable balance of design size and efficiency. Additionally, the typical component selection table in the TPS7H4010-SEP data sheet is consulted to make sure the values are close to the recommended selection. This is confirmed through a load step and Bode plot measurement as shown in Section 4.3.2. A 50Ω resistor is placed in series with the top feedback resistor and an option for a feed-forward capacitor is implemented to enable easier measuring and optimization of the control loop.

Next, the output voltage ripple is determined. First the inductor ripple is calculated as shown in Equation 15. An inductor ripple current of 1.33A is calculated.

Equation 15. I L ( r i p p l e ) = V I N - V O U T L × V O U T V I N ×   f S W

where

  • VIN is the input voltage, 12V
  • VOUT is the configured output voltage, 3.3V
  • L is the selected inductor, 1.8µH
  • fSW is the selected operating frequency, 1MHz

Next, one 100µF electrolytic capacitor and two 22µF ceramic capacitors are selected. Using the K-SIM tool from Kemet, the output impedance of these parallel capacitors at 1MHz is determined to be approximately 12.2mΩ. Multiplying the impedance by the inductor ripple current gives the approximated output ripple of ±16.2mV.

Finally, the output voltage is configured using a resistor divider connected to the feedback pin. An RFB_TOP of 50.55kΩ (50.5kΩ in series with a 50Ω) and RFB_BOT of 22.1kΩ are selected which results in a nominal output voltage of 3.307V. Using the data sheet feedback voltage parameter 0.987V minimum and 1.017V maximum along with 0.1% resistor tolerances (using a sum of squares to get ±0.14% error contribution), the overall DC accuracy can be approximated using Equation 16 and Equation 17. The accuracy is calculated to be –1.82% and +1.45%.

Equation 16. E r r o r ( p o s i t i v e ) = V F B ( m a x ) × R F B _ T O P + R F B _ B O T R F B _ B O T - V O U T ( i d e a l ) V O U T ( i d e a l ) + R ( e r r o r )
Equation 17. E r r o r ( n e g a t i v e ) = V F B ( m i n ) × R F B _ T O P + R F B _ B O T R F B _ B O T - V O U T ( i d e a l ) V O U T ( i d e a l ) - R ( e r r o r )

One additional consideration for accuracy is if auto mode is enabled. Auto mode results in higher efficiency at light loads at the expense of worse load regulation. Consulting the TPS7H4010-SEP load and line regulation image in the TPS7H4010-SEP data sheet and looking at the approximate 0.08V increase at light load for a 5V application, auto mode is approximated to add an additional error of +1.6%. Therefore, if auto mode is enabled, the accuracy is –1.82% and +3.05%. This error is acceptable for this rail, and therefore auto mode is enabled.

Table 3-6 shows a summary of these calculations.

Table 3-6 3V3_VCCO Rail Design Values
PARAMETER DESCRIPTION OR TYPICAL VALUE
VIN 12V
VOUT 3.3V
IOUT(max) 6A
fSW, switching frequency 1MHz
DC Accuracy –1.82%, +3.05%
Output ripple 16.2mVpp
LSW, output inductor 1.8μH XAL6030-182ME_
COUT, output capacitance 1x100µF T520B, 2x22µF ceramic
CIN, input capacitance 2x10µF ceramic, 1x470nF ceramic
tSS, soft start time 6.3ms (SS float)
Bias connection Connected to output 3V3_VCCO
Mode Auto enabled
TIDA-050088 3V3_VCCO Schematic Figure 3-13 3V3_VCCO Schematic
TIDA-050088 3V3_VCCO Layout Figure 3-14 3V3_VCCO Layout