TIDUFB3 July   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS7H5006-SEP
      2. 2.3.2 TPS7H6025-SEP
      3. 2.3.3 TPS7H1111-SEP
      4. 2.3.4 TPS7H4010-SEP
      5. 2.3.5 TPS73801-SEP
      6. 2.3.6 TPS7H3302-SEP
      7. 2.3.7 TPS7H3014-SEP
      8. 2.3.8 TPS7H2221-SEP
      9. 2.3.9 SN54SC6T14-SEP
  9. 3System Design Theory
    1. 3.1 0V8 Discrete Buck Regulator (VCCINT)
      1. 3.1.1 VCCINT Load Step
    2. 3.2 Buck Regulators (Integrated)
      1. 3.2.1 1V2
      2. 3.2.2 1V2_VCCO
      3. 3.2.3 1V2_MEM
      4. 3.2.4 2V5_DDR_VPP
      5. 3.2.5 3V3_VCCO
    3. 3.3 Linear Regulators
      1. 3.3.1 DDR Termination
      2. 3.3.2 0V92
      3. 3.3.3 1V5_GTY
      4. 3.3.4 1V5
      5. 3.3.5 5V0_SYS
    4. 3.4 Sequencing
      1. 3.4.1 TPS7H3014-SP Sequencer
      2. 3.4.2 TPS7H2221-SEP Discharge Circuit
      3. 3.4.3 VCCINT Discharge Circuit
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Discrete Buck Regulator (VCCINT)
        1. 4.3.1.1 0V8
      2. 4.3.2 Buck Regulators (Integrated)
        1. 4.3.2.1 1V2
        2. 4.3.2.2 1V2_VCCO
        3. 4.3.2.3 1V2_MEM
        4. 4.3.2.4 2V5_DDR_VPP
        5. 4.3.2.5 3V3_VCCO
      3. 4.3.3 Linear Regulators
        1. 4.3.3.1 0V6_VTT
        2. 4.3.3.2 0V92
        3. 4.3.3.3 1V5_GTY
        4. 4.3.3.4 1V5
        5. 4.3.3.5 5V0_SYS
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 Layout Prints
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  12. 6About the Author

3.2.2 1V2_VCCO

The TPS7H4010-SEP synchronous buck converter is selected to generate the required 1.2V directly from the 12V rail. While the TPS7H4010-SEP is capable of 6A, the Versal Edge XPIO (bank 7xx) rails only require 2A. Additionally, the 1V2_VCCO output feeds the input of the TPS7H1111-SEP for the 0V92 rail which is up to another 1A. Therefore, the design decision is to size this design for 4A to provide reasonable margin.

A switching frequency of 1MHz and a 0.8μH XAL5030-801ME_ inductor are selected to provide a reasonable balance of design size and efficiency. Additionally, the typical component selection table in the TPS7H4010-SEP data sheet is consulted to make sure the values are close to the recommended selection. This is confirmed through a load step and Bode plot measurement as shown in Section 4.3.2. A 50Ω resistor is placed in series with the top feedback resistor and an option for a feed-forward capacitor is implemented to enable easier measuring and optimization of the control loop.

Next output voltage ripple is determined. First the inductor ripple is calculated as shown in Equation 6. An inductor ripple current of 1.35A is calculated.

Equation 6. I L ( r i p p l e ) = V I N - V O U T L × V O U T V I N ×   f S W

where

  • VIN is the input voltage, 12V
  • VOUT is the configured output voltage, 1.2V
  • L is the selected inductor, 0.8µH
  • fSW is the selected operating frequency, 1MHz

Next, two 100µF electrolytic capacitors and one 22µF ceramic capacitor are selected. Using the K-SIM tool from Kemet, the output impedance of these parallel capacitors at 1MHz is determined to be approximately 4.2mΩ. Multiplying the impedance by the inductor ripple current gives the approximated output ripple of ±5.7mV.

Finally, the output voltage is configured using a resistor divider connected to the feedback pin. An RFB_TOP of 50.55kΩ (50.5kΩ in series with a 50Ω) and RFB_BOT of 261kΩ are selected which results in a nominal output voltage of 1.201V. Using the data sheet feedback voltage parameter 0.987V minimum and 1.017V maximum along with 0.1% resistor tolerances (using a sum of squares to get ±0.14% error contribution), the overall DC accuracy can be approximated using Equation 7 and Equation 8. The accuracy is calculated to be –1.96% and +1.30%.

Equation 7. E r r o r ( p o s i t i v e ) = V F B ( m a x ) × R F B _ T O P + R F B _ B O T R F B _ B O T - V O U T ( i d e a l ) V O U T ( i d e a l ) + R ( e r r o r )
Equation 8. E r r o r ( n e g a t i v e ) = V F B ( m i n ) × R F B _ T O P + R F B _ B O T R F B _ B O T - V O U T ( i d e a l ) V O U T ( i d e a l ) - R ( e r r o r )

One additional consideration for accuracy is if auto mode is enabled. Auto mode results in higher efficiency at light loads at the expense of worse load regulation. Consulting the TPS7H4010-SEP load and line regulation figure in the TPS7H4010-SEP data sheet and looking at the approximate 0.08V increase at light load for a 5V application, auto mode is approximated to add an additional error of +1.6%. Therefore, if auto mode is enabled, the accuracy is –1.96% and +2.90%. This error is acceptable for this rail, and therefore auto mode is enabled.

Note that the output connector shows a current of 2A. This is because when all rails are fully loaded, 2A is outputted for the Versal Edge 1V2_VCCO rail while the other 2A is provided to other internal rails. The board connectors themselves are sized to support 4A.

Table 3-3 shows a summary of these calculations.

Table 3-3 1V2_VCCO Rail Design Values
PARAMETER DESCRIPTION OR TYPICAL VALUE
VIN 12V
VOUT 1.2V
IOUT(max) 4A
fSW, switching frequency 1MHz
DC Accuracy –1.96%, +2.90%
Output ripple 5.7mVpp
LSW, output inductor 0.8µH, XAL5030-801ME_
COUT, output capacitance 2x100µF T520B, 1x22µF ceramic
CIN, input capacitance 3x10µF ceramic, 1x470nF ceramic
tSS, soft start time 6.3ms (SS float)
Bias connection Connected to external 3V3_VCCO
Mode Auto enabled
TIDA-050088 1V2_VCCO Schematic Figure 3-7 1V2_VCCO Schematic
TIDA-050088 1V2_VCCO Layout Figure 3-8 1V2_VCCO Layout