TIDUFE5 July   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1  TMS320F2800137
      2. 2.3.2  LMG3651R025
      3. 2.3.3  LMG2650
      4. 2.3.4  TMCS1126
      5. 2.3.5  ISO6721
      6. 2.3.6  UCC28881
      7. 2.3.7  UCC27712
      8. 2.3.8  TPS562206
      9. 2.3.9  TLV9062
      10. 2.3.10 TLV74033
  9. 3System Design Theory
    1. 3.1 Totem Pole PFC
      1. 3.1.1 Inductor Ratings
      2. 3.1.2 AC Voltage Sensing
      3. 3.1.3 DC Link Voltage Sensing
      4. 3.1.4 AC Current Sensing
      5. 3.1.5 DC Link Capacitor Rating
    2. 3.2 Three-Phase PMSM Drive
      1. 3.2.1 Field Oriented Control of PM Synchronous Motor
        1. 3.2.1.1 Space Vector Definition and Projection
        2. 3.2.1.2 Clarke Transformation
        3. 3.2.1.3 Park Transformation
        4. 3.2.1.4 Basic Scheme of FOC for AC Motor
        5. 3.2.1.5 Rotor Flux Position
      2. 3.2.2 Sensorless Control of PM Synchronous Motor
        1. 3.2.2.1 Enhanced Sliding Mode Observer With Phase Locked Loop
          1. 3.2.2.1.1 Mathematical Model and FOC Structure of an IPMSM
          2. 3.2.2.1.2 Design of ESMO for the IPMSM
          3. 3.2.2.1.3 Rotor Position and Speed Estimation With PLL
      3. 3.2.3 Hardware Prerequisites for Motor Drive
        1. 3.2.3.1 Current Sensing With Three-Shunt
        2. 3.2.3.2 Motor Voltage Feedback
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Hardware Board Overview
      2. 4.1.2 Test Conditions
      3. 4.1.3 Test Equipment Required for Board Validation
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Functional Waveforms
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
      3. 5.1.3 Altium Project
      4. 5.1.4 Gerber Files
      5. 5.1.5 PCB Layout Recommendations
    2. 5.2 Tools
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

5.1.5 PCB Layout Recommendations

This reference design is implemented using a PCB with two layer, 1oz copper with a single-side SMD component placement considering the cost sensitivity of the application. There are several important aspects to remember while designing the PCB. In the following list, system-level placement and layout of each block is explained.

Components in the high-power path are kept on the outer edges of the PCB using the minimum distance possible. The microcontroller is placed at the center considering the optimum distance from all the power blocks that need to be controlled. Pin assignment is set to minimize the control signal trace and feedback signal trace distance and the crossing between analog and digital signals.

  • AC Line Protection and EMI Filter
    • AC line protection components are closely placed within the minimum distance of the connection path. Earth connection guarding is provided around the protection and EMI filter circuit.
    • An active EMI filter is placed at the optimum distance so as to stay closer to switching and to have the minimum distance to connect to the EARTH terminal.
  • IPFC Drive

    In IPFC drive, three current paths are very critical for PCB layout - the high power AC loop, DC loop, and gate drive loop. These paths need to be short with the maximum width possible to reduce parasitic-loop inductance.

    • AC loop – Consists of diode bridge (source), inductor, and MOSFET drain and MOSFET source (return). On this loop, especially the connection between the inductor, the MOSFET Drain and Diode Anode handle high frequency and high power. Special care is taken while connecting this node to minimize parasitic inductance by reducing the distance and increasing the copper area.
    • DC loop – Consists of diode bridge (source), inductor, diode, capacitor, load (return). To distribute the RMS current stress evenly, place the bank of electrolyte capacitors such that the electrical distance of each one from the diode cathodes remains approximately the same. This design uses a copper plane for the VDC and PGND connection. To suppress the high-frequency component, a metal-film capacitor is placed just next to the cathode of the diode. The capacitor minimizes the loop inductance significantly.
    • Gate drive loop – Consists of driver power supply (source), gate driver IC, MOSFET gate, and MOSFET source pin (return). This design uses parallel arrangement for two phases of IPFC to minimize the other two AC/DC loops. Because of this parallel arrangement, the outer phase MOSFET gate is inaccessible to the gate driver. An SMD insulated thick jumper is used to connect the gate driver signal to MOSFET gate.
  • Compressor and Fan Drive
    • With the highest ripple requirement, a compressor drive is placed closest to the DC bus capacitor bank of the IPFC drive and a fan is placed next to the compressor.
    • The low-side shunt resistor method with 4-wire sensing is implemented for current sensing. A differential pair with impedance matching resistors is used to connect the sensing signal from the shunt resistors to the op-amp circuit. Shunt resistors are placed near the module with an immediate ground copper plane connection.
  • Auxiliary Power Supply
    • With the lowest power and ripple requirement, auxiliary power is placed after the fan drive. A dedicated copper plane is used to connect the APS ground to the DC bus capacitor bank. This arrangement minimizes interference between the high frequency and high power motor current and control circuit.