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DS90LT012AQ-Q1

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Automotive LVDS differential line receiver

Data sheet
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Automotive LVDS differential line receiver

DS90LT012AQ-Q1

ACTIVE
Data sheet Order now

Product details

Parameters

Function Receiver Protocols LVDS, CML, LVPECL Number of transmitters 0 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS, CML, LVPECL Output signal CMOS Rating Automotive Operating temperature range (C) -40 to 125 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • AECQ-100 Grade 1
  • -40 to +125°C Temperature Range Operation
  • Compatible with ANSI TIA/EIA-644-A Standard
  • >400 Mbps (200 MHz) Switching Rates
  • 100 ps Differential Skew (Typical)
  • 3.5 ns Maximum Propagation Delay
  • Integrated Line Termination Resistor (100Ω Typical)
  • Single 3.3V power supply design
  • Power Down High Impedance on LVDS Inputs
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Pinout Simplifies PCB Layout
  • Low Power Dissipation (10mW Typical@ 3.3V Static)
  • SOT-23 5-Lead Package

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Description

The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology

The DS90LT012AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AQ includes an input line termination resistor for point-to-point applications.

The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications.

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Technical documentation

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Type Title Date
* Data sheet DS90LT012AQ Automotive LVDS Differential Line Receiver datasheet (Rev. E) Apr. 17, 2013
Application note LVDS to Improve EMC in Motor Drives Sep. 27, 2018
Application note How Far, How Fast Can You Operate LVDS Drivers and Receivers? Aug. 03, 2018
Application note AN-1821 CPRI Repeater System (Rev. A) Apr. 26, 2013
Application note An Overview of LVDS Technology Oct. 05, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
99
Description
The DS90LV047-48AEVM is an evaluation module (EVM) designed for performance and functional evaluation of Texas Instruments' DS90LV047A 3-V LVDS quad CMOS differential line driver and DS90LV048A 3-V LVDS CMOS differential line receiver. With this kit, users can quickly evaluate the output (...)
Features
  • DS90LV047A:  Converts single-ended LVCMOS to differential LVDS
  • DS90LV048A:  Converts differential LVDS to single-ended LVCMOS
  • Greater than 400-Mbps (200 MHz) switching rates
  • Single-supply operation:  3.3 V
View details

Design tools & simulation

SIMULATION MODEL Download
SNLM044.ZIP (11 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
View details
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI — TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

Reference designs

リファレンス・デザイン Download
Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
TIDA-010122 — This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA (...)
document-generic Schematic
リファレンス・デザイン Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-generic Schematic
リファレンス・デザイン Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic
リファレンス・デザイン Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic
リファレンス・デザイン Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SOT-23 (DBV) 5 View options

Ordering & quality

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