SN74LV244A

ACTIVE

Product details

Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 16 ICC (Max) (uA) 20 IOH (Max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 16 ICC (Max) (uA) 20 IOH (Max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog
SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 29 mm² 6.5 x 4.4 TSSOP (PW) 20 29 mm² 4.4 x 6.5 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 16 mm² 3.5 x 4.5
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Drop-in replacement with upgraded functionality to the compared device.
SN74LV244A-EP ACTIVE Enhanced product 8-ch, 2-V to 5.5-V buffers with 3-state outputs

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SN74LV244AT ACTIVE 8-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

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Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV244A Behavioral SPICE Model

SCEM653.ZIP (7 KB) - PSpice Model
Simulation model

SN74LV244A IBIS Model (Rev. A)

SCEM137A.ZIP (24 KB) - IBIS Model
Reference designs

TIDEP0022 — ARM MPU with Integrated BiSS C Master Interface Reference Design

Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0035 — ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design

This reference design implements HIPERFACE DSL master protocol on Industrial Communication Sub-System (PRU-ICSS). The two-wire interface allows integration of position feedback wires into motor cable.  It consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0050 — EnDat 2.2 System Reference Design

This reference design implements EnDat 2.2 Master protocol stack and hardware interface based on HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of EnDat 2.2 Master protocol stack, half-duplex communications using RS-485 transceivers and the line termination (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDEP0054 — Parallel Redundancy Protocol (PRP) Ethernet Reference Design for Substation Automation

This is a reference design for high-reliability, low-latency network communications for substation automation equipment in smart grid transmission and distribution networks. It supports the parallel redundancy protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This reference (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options
VQFN (RGY) 20 View options

Ordering & quality

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  • Ongoing reliability monitoring

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