Home Logic Buffer/driver Non-Inverting buffer/driver

SN74LV244A

ACTIVE
Order now

Octal Buffers/Drivers With 3-State Outputs

Data sheet
Top
Octal Buffers/Drivers With 3-State Outputs

SN74LV244A

ACTIVE
Data sheet Order now

Product details

Parameters

Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 8 IOL (Max) (mA) 16 IOH (Max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 220 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 42 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 16 mm² 3.5 x 4.5 open-in-new Find other Non-Inverting buffer/driver

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250-mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
 open-in-new Find other Non-Inverting buffer/driver

Description

The SN74LV244A octal buffers and line drivers are designed for 2-V to 5.5-V VCC operation.

The SN74LV244A devices are designed specifically to improve both performance and density of the 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs.

 open-in-new Find other Non-Inverting buffer/driver
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 1
Type Title Date
* Datasheet SN74LV244A Octal Buffers and Drivers With 3-State Outputs datasheet (Rev. N) Oct. 15, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Design tools & simulation

SIMULATION MODELS Download
SCEM137A.ZIP (24 KB) - IBIS Model
SIMULATION MODELS Download
SCEM653.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
ARM MPU with Integrated BiSS C Master Interface Reference Design
TIDEP0022 — Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035 — Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable.  Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
EnDat 2.2 System Reference Design
TIDEP0050 — The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Parallel Redundancy Protocol (PRP) Ethernet Reference Design for Substation Automation
TIDEP0054 — This TI Design implements a solution for high-reliability, low-latency network communications for substation automation equipment in Smart Grid transmission and distribution networks. It supports the Parallel Redundancy Protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options
VQFN (RGY) 20 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Training series

View all TI training and videos

Videos

Related videos