8-ch, 2-V to 5.5-V buffers with 3-state outputs
Product details
Parameters
Package | Pins | Size
Features
- 2-V to 5.5-V VCC Operation
- Max tpd of 6.5 ns at 5 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C - Support Mixed-Mode Voltage Operation on All
Ports - Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250-mA Per
JESD 17 - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Description
The SN74LV244A octal buffers and line drivers are designed for 2-V to 5.5-V VCC operation.
The SN74LV244A devices are designed specifically to improve both performance and density of the 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs.
Technical documentation
= Top documentation for this product selected by TI
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SN74LV244A Octal Buffers and Drivers With 3-State Outputs datasheet (Rev. N) | Oct. 15, 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
14-24-LOGIC-EVM
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
14-24-NL-LOGIC-EVM
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic and translation devices with included dual supply support
- Board has 9 sections that can be broken apart for a smaller form factor
Design tools & simulation
SCEM137A.ZIP (24 KB) - IBIS Model
SCEM653.ZIP (7 KB) - PSpice Model
Reference designs
TIDEP0022 — Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
TIDEP0035 — Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable. Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
Design files
-
download AM437x/AMIC120 Industrial Development Kit (IDK) Gerber Files (Rev. A).zip (11389KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Assembly Drawing Files (Rev. A).zip (870KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Design Files (CAD) (Rev. A).zip (21148KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Layer Plots (Rev. A).zip (6065KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Bill of Materials (BOM) (Rev. A).zip (580KB)
TIDEP0050 — The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and (...)
Design files
-
download EnDAT 2.2 System BOM.pdf (119KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Gerber Files (Rev. A).zip (11389KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Assembly Drawing Files (Rev. A).zip (870KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Design Files (CAD) (Rev. A).zip (21148KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Layer Plots (Rev. A).zip (6065KB)
TIDEP0054 — This TI Design implements a solution for high-reliability, low-latency network communications for substation automation equipment in Smart Grid transmission and distribution networks. It supports the Parallel Redundancy Protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This (...)
Design files
-
download Parallel Redundancy Protocol Ethernet for Substation Automation BOM.pdf (135KB) -
download Parallel Redundancy Protocol Ethernet for Substation Automation Assembly Drawing.pdf (1192KB) -
download Parallel Redundancy Protocol Ethernet for Substation Automation Layer Plots.pdf (1366KB) -
download Parallel Redundancy Protocol Ethernet for Substation Automation CAD Files.zip (3014KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SO (NS) | 20 | View options |
SOIC (DW) | 20 | View options |
SSOP (DB) | 20 | View options |
TSSOP (PW) | 20 | View options |
TVSOP (DGV) | 20 | View options |
VQFN (RGY) | 20 | View options |
Ordering & quality
Information included:
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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