Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DSF) 6 1 mm² 1 x 1
  • Dual Open-Drain Buffer Configuration
  • -24-mA Output Drive at 3.3 V
  • Support Translation-Up and Down
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs and Open-Drain Outputs Accept Voltages
    Up to 5.5 V
  • Max tpd of 3.7 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Dual Open-Drain Buffer Configuration
  • -24-mA Output Drive at 3.3 V
  • Support Translation-Up and Down
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs and Open-Drain Outputs Accept Voltages
    Up to 5.5 V
  • Max tpd of 3.7 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual buffer and driver is designed for 1.65-V to 5.5-V VCC operation. The output of the SN74LVC2G07 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual buffer and driver is designed for 1.65-V to 5.5-V VCC operation. The output of the SN74LVC2G07 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC2G07 Dual Buffer and Driver With Open-Drain Outputs datasheet (Rev. L) PDF | HTML 22 May 2015
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

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User guide: PDF
Not available on TI.com
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User guide: PDF | HTML
Not available on TI.com
Driver or library

SPRCAE5 Metrology Library and Software for Concerto F28M35H52C

Supported products & hardware

Supported products & hardware

Products
C2000 real-time microcontrollers
F28M35H52C C2000™ dual core 32-bit MCU with 250 MIPS, 1024-kb Flash F28M35H52C-Q1 Automotive C2000™ dual-core 32-bit MCU with 250 MIPS, 1024 KB flash
Linear & low-dropout (LDO) regulators
TLV1117 800-mA, 15-V, linear voltage regulator
Noninverting buffers & drivers
SN74LVC2G07 2-ch, 1.65-V to 5.5-V buffers with open-drain outputs
Programmable & variable gain amplifiers (PGAs & VGAs)
PGA112 Zero-drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp with 2-ch mux
Precision op amps (Vos<1mV)
OPA4376 Quad precision, low-noise, low quiescent current operational amplifier
Power op amps
AFE032 Low-cost, integrated, powerline communications (PLC) analog front-end for driving low-impedance line
Simulation model

SN74LVC2G07 Behavioral SPICE Model

SCEM621.ZIP (7 KB) - PSpice Model
Simulation model

SN74LVC2G07 IBIS Model (Rev. E)

SCEM254E.ZIP (24 KB) - IBIS Model
Reference designs

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The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly connecting to a three phase ACI or PMSM motor. Many drive topologies can be created from the combined control, power and communications technologies included on this single platform.  Includes (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01487 — Isolated CAN Flexible Data (FD) Rate Repeater Reference Design

CAN and CANopen are legacy Fieldbus protocols used in many applications in factory automation. Whenever high voltage can damage the end equipment, there is need for isolation. This isolated CAN flexible data (FD) rate repeater reference design adds electrical isolation between two CAN (...)
Design guide: PDF
Schematic: PDF
Reference designs

PMP40690 — 4-kW interleaved CCM totem pole bridgeless PFC reference design using C2000™ MCU and GaN

This reference design is a 4-kW interleaved CCM totem pole (TTPL) bridgeless PFC reference design using a 64-pin C2000™ microcontroller, LM3410 gallium nitride device and TMCS1100 hall sensor. It is based on TIDM-02008 bidirectional interleaved CCM TTPL bridgeless PFC reference (...)
Test report: PDF
Schematic: PDF
Reference designs

TIDA-060001 — SunSpec Rapid Shutdown Transmit and Receive Reference Design

This reference design interfaces an AFE031 Powerline Communications Analog Front End with a C2000 MCU to send and receive data over a wired coupled interface using frequency shift keying (FSK). The design demonstrates the SunSpec standard protocol transmitting the specific 33-bit word packet using (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01572 — Stereo Evaluation Module Reference Design of the Digital Input, Class-D, IV Sense Audio Amplifier

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Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
DSBGA (YZP) 6 Ultra Librarian
SOT-23 (DBV) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian

Ordering & quality

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  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

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