Product details

Number of channels (#) 1 Total supply voltage (Min) (+5V=5, +/-5V=10) 2.5 Total supply voltage (Max) (+5V=5, +/-5V=10) 5.5 BW @ Acl (MHz) 36 Acl, min spec gain (V/V) 1 Slew rate (Typ) (V/us) 220 Architecture Fully Differential ADC Driver, Bipolar Vn at flatband (Typ) (nV/rtHz) 10 Iq per channel (Typ) (mA) 0.25 Rail-to-rail In to V-, Out Vos (offset voltage @ 25 C) (Max) (mV) 0.4 Operating temperature range (C) -40 to 125 Output current (Typ) (mA) 26 2nd harmonic (dBc) 129 3rd harmonic (dBc) 138 @ MHz 0.001 GBW (Typ) (MHz) 27 Input bias current (Max) (pA) 250000 Features Shutdown CMRR (Typ) (dB) 116 Rating Catalog
Number of channels (#) 1 Total supply voltage (Min) (+5V=5, +/-5V=10) 2.5 Total supply voltage (Max) (+5V=5, +/-5V=10) 5.5 BW @ Acl (MHz) 36 Acl, min spec gain (V/V) 1 Slew rate (Typ) (V/us) 220 Architecture Fully Differential ADC Driver, Bipolar Vn at flatband (Typ) (nV/rtHz) 10 Iq per channel (Typ) (mA) 0.25 Rail-to-rail In to V-, Out Vos (offset voltage @ 25 C) (Max) (mV) 0.4 Operating temperature range (C) -40 to 125 Output current (Typ) (mA) 26 2nd harmonic (dBc) 129 3rd harmonic (dBc) 138 @ MHz 0.001 GBW (Typ) (MHz) 27 Input bias current (Max) (pA) 250000 Features Shutdown CMRR (Typ) (dB) 116 Rating Catalog
SOIC (D) 8 19 mm² 4.9 x 3.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 WQFN (RUN) 10 4 mm² 2 x 2
  • Ultra Low-Power:
    • Voltage: 2.5 V to 5.5 V
    • Current: 250 µA
    • Power-Down Mode: 0.5 µA (Typical)
  • Fully Differential Architecture
  • Bandwidth: 36 MHz (Av = 1 V/V)
  • Slew Rate: 200 V/µs
  • THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
  • Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
  • High DC Accuracy:
    • VOS: ±100 µV
    • VOS Drift: ±3 µV/˚C (–40°C to +125°C)
    • AOL: 114 dB
  • Rail-to-Rail Output (RRO)
  • Negative Rail Input (NRI)
  • Output Common-Mode Control
  • 8-Pin SOIC (D) and VSSOP (DGK)
  • 10-Pin WQFN (RUN)
  • Ultra Low-Power:
    • Voltage: 2.5 V to 5.5 V
    • Current: 250 µA
    • Power-Down Mode: 0.5 µA (Typical)
  • Fully Differential Architecture
  • Bandwidth: 36 MHz (Av = 1 V/V)
  • Slew Rate: 200 V/µs
  • THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
  • Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
  • High DC Accuracy:
    • VOS: ±100 µV
    • VOS Drift: ±3 µV/˚C (–40°C to +125°C)
    • AOL: 114 dB
  • Rail-to-Rail Output (RRO)
  • Negative Rail Input (NRI)
  • Output Common-Mode Control
  • 8-Pin SOIC (D) and VSSOP (DGK)
  • 10-Pin WQFN (RUN)

The THS4531A device is a low-power, fully differential amplifier with input common-mode range below the negative rail and rail-to-rail output. The device is designed for low-power data acquisition systems and high-density applications where power consumption and dissipation is critical.

The device features accurate output common-mode control that allows for DC coupling when driving analog-to-digital converters (ADCs). This control, coupled with the input common-mode range below the negative rail and rail-to-rail output, allows for easy interface from single-ended ground-referenced signal sources to successive-approximation registers (SARs), and delta-sigma (ΔΣ) ADCs using only single-supply 2.5-V to 5-V power. The THS4531A is also a valuable tool for general-purpose, low-power differential signal conditioning applications.

The THS4531A device is a low-power, fully differential amplifier with input common-mode range below the negative rail and rail-to-rail output. The device is designed for low-power data acquisition systems and high-density applications where power consumption and dissipation is critical.

The device features accurate output common-mode control that allows for DC coupling when driving analog-to-digital converters (ADCs). This control, coupled with the input common-mode range below the negative rail and rail-to-rail output, allows for easy interface from single-ended ground-referenced signal sources to successive-approximation registers (SARs), and delta-sigma (ΔΣ) ADCs using only single-supply 2.5-V to 5-V power. The THS4531A is also a valuable tool for general-purpose, low-power differential signal conditioning applications.

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Technical documentation

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Type Title Date
* Data sheet THS4531A Ultra Low-Power, Rail-to-Rail Output, Fully Differential Amplifier datasheet (Rev. D) 04 Mar 2020
Application note Maximizing System Total Harmonic Distortion Using High Speed Amplifiers 20 Jun 2018
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mar 2017
Technical article How to minimize filter loss when you drive an ADC 20 Oct 2016
Application note Fully-Differential Amplifiers (Rev. E) 19 Sep 2016
Technical article Go differential to differentiate your precision design 11 Aug 2016
Technical article How to use a fully differential amplifier as a level shifter 13 Jul 2016
Technical article What you need to know about internal ESD protection on integrated circuits 02 Dec 2015
EVM User's guide THS4531ADGKEVM Evaluation Module 05 Dec 2012
Analog Design Journal Using fully differential op amps as attenuators, Part 3 04 Oct 2009
Analog Design Journal Using fully differential op amps as attenuators, Part 2 14 Jul 2009
Analog Design Journal Using fully differential op amps as attenuators, Part 1 01 May 2009
Analog Design Journal Analysis of fully differential amplifiers 11 Mar 2005
Analog Design Journal Designing for low distortion with high-speed op amps 02 Mar 2005
Application note Noise Analysis for High Speed Op Amps (Rev. A) 17 Jan 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

THS4531ADGKEVM — THS4531ADGKEVM Evaluation Module

The THS4531ADGKEVM is designed to quickly and easily demonstrate the functionality and versatility of the amplifier. The EVM is ready to connect to power, signal source, and test instruments through the use of on-board connectors. The default amplifier configuration is single-ended input, (...)

Simulation model

THS4531 TINA-TI Reference Design

SLOM262.TSC (3751 KB) - TINA-TI Reference Design
Simulation model

THS4531A PSpice Model (Rev. A)

SLOM350A.ZIP (277 KB) - PSpice Model
Simulation model

THS4531A TINA-TI Spice Model (Rev. A)

SLOM351A.ZIP (15 KB) - TINA-TI Spice Model
Simulation model

THS4531A TINA-TI Reference Design (Rev. A)

SLOM352A.TSC (68 KB) - TINA-TI Reference Design
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Calculation tool

TI FDA Calculator

SBOR022.ZIP (1639 KB)
Bill of materials (BOM)

THS4531ADGK EVM Design Files

SLOR110.ZIP (315 KB)
Reference designs

TIDA-00202 — Interface to a HIPERFACE Position Encoder Reference Design

The TIDA-00202 reference design implements an EMC compliant industrial hybrid analog and digital interface to a HIPERFACE position encoder. A 3.3V supply RS485 transceiver with IEC-ESD and IEC-EFT protection is used for the bidirectional parameter channel. For the analog sin/cos signal (...)
Reference designs

TIDA-00176 — Interface to Sin/Cos Encoders with High-Resolution Position Interpolation Reference Design

The TIDA-00176 reference design is an EMC compliant industrial interface to Sin/Cos position encoders. Applications include industrial drives, which require accurate speed and position control.
The design utilizes a 16-bit dual sample ADC with drop-in compatible 14- or 12-bit versions available, (...)
Reference designs

TIDA-00178 — Interface to a Sin/Cos Encoder with Sitara AM437x Reference Design

The TIDA-00178 reference design is an EMC compliant industrial interface to Sin/Cos position encoders. Applications include industrial drives, which require accurate speed and position control.

The design utilizes a 16-bit dual sample ADC with drop-in compatible 14- or 12-bit versions available, (...)

Reference designs

TIDA-00368 — Reference Design for Interfacing Current Output Hall Sensors and CTs with Differential ADC/MCU

This reference design provides interfacing current output Hall sensors and current transformers to differential ADC (standalone and integrated into MCU). The differential signal conditioning circuit is designed to measure motor current with an accuracy of ±0.5% across operating (...)
Reference designs

TIDA-00187 — Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts

Operational amplifiers (op amps) have been used for decades in signal conditioning circuits and measurement systems. An op amp that has an output spanning from negative to positive supply rail are generally referred to as rail-to-rail output (RRO) op amps. These devices have been used increasingly (...)
Package Pins Download
QFN (RUN) 10 View options
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

Ordering & quality

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