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Product details

Parameters

Arm CPU 0 Arm MHz (Max.) 0 DSP 1 C64x Operating system DSP/BIOS, VLX Video acceleration 1 VICP Video port (configurable) 5 16-Bit Dual-Ch On-chip L2 cache/RAM 512 KB(DSP) DRAM DDR2 PCI/PCIe 1 32-Bit [66 MHz] Ethernet MAC 0 USB 0 SPI 0 I2C 1 UART (SCI) 0 Display type 5 Video Ports Operating temperature range (C) -40 to 105, -40 to 90, 0 to 90 Rating Catalog open-in-new Find other Audio & media processors

Package | Pins | Size

FCBGA (ZUT) 529 361 mm² 19 x 19 open-in-new Find other Audio & media processors

Features

  • High-Performance Digital Media Processor
    • 720-MHz, 800-MHz, 900-MHz, 1.1-GHz C64x+™ Clock Rates
    • 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900), 0.91 ns (-1100) Instruction Cycle Time
    • 5760, 6400, 7200, 8800 MIPS
    • Eight 32-Bit C64x+ Instructions/Cycle
    • Fully Software-Compatible With C64x/Debug
    • Commercial Temperature Ranges (-720, -900, and -1100 only)
    • Extended Temperature Ranges (-800 only)
    • Industrial Temperature Ranges (-720, -900, and -1100 only)
  • VelociTI.2™ Extensions to VelociTI™
    Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-bit Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-bit Data)
    • 8-bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-bit (32K-byte) L1P Program RAM/Cache [Direct Mapped]
    • 256K-bit (32K-byte) L1D Data RAM/Cache
      [2-Way Set-Associative]
    • 2M-bit/256K-byte (DM647) or 4M-Bit/512K-byte) (DM648) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Five Configurable Video Ports
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions/Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O)
    • Asynchronous 16-Bit Wide EMIF (EMIFA)
      • Up to 128M-Byte Total Address Reach
      • 64M-Byte Address Reach per CE Space
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM)
    • Synchronous Memories (SBSRAM and ZBT SRAM)
    • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 3-Port Gigabit Ethernet Switch Subsystem
  • Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One UART (With RTS and CTS Flow Control)
  • One 4-wire Serial Port Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Multichannel Audio Serial Port (McASP)
    • Ten Serializers and SPDIF (DIT) Mode
  • 16/32-Bit Host-Port Interface (HPI)
  • Advanced Event Triggering (AET) Compatible
  • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3
  • VLYNQ™ Interface (FPGA Interface)
  • On-Chip ROM Bootloader
  • Individual Power-Saving Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 32 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Package:
    • 529-pin nFBGA (ZUT suffix)
    • 19x19 mm 0.8 mm pitch BGA
    • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -800, -900, -1100)
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Description

The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM647, DM648 devices are based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 4400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the C64x+ DSP, see the (literature number SPRU732).

The devices also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M-bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and VP4). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII ports (DM648) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; four 64-bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.

The video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

The video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the video port peripherals, see the (literature number SPRUEM1).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 33
Type Title Date
* Datasheet TMS320DM647/TMS320DM648 Digital Media Processors datasheet (Rev. H) Apr. 10, 2012
* Errata TMS320DM647, TMS320DM648 Digital Media Processors Silicon Errata (Rev. G) Nov. 01, 2011
User guides Emulation and Trace Headers Technical Reference Manual (Rev. I) Aug. 09, 2012
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port UG (Rev. B) Nov. 12, 2010
Application notes TMS320DM647/8 Power Consumption Summary (Rev. B) Jan. 06, 2010
Application notes Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms Sep. 24, 2009
User guides TMS320DM647/DM648 DSP 3 Port Switch Ethernet Subsystem User's Guide (Rev. B) Jul. 14, 2009
User guides TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) Jul. 02, 2009
Application notes TMS320DM648/7 SoC Architecture and Throughput Overview Jun. 12, 2009
Application notes Using the TMS320DM647/DM648 Bootloader (Rev. D) Jun. 01, 2009
User guides TMS320DM647/DM648 DSP Subsystem User's Guide (Rev. B) Apr. 24, 2009
User guides TMS320DM647DM648 DSP 64-Bit Timer User's Guide (Rev. B) Mar. 10, 2009
User guides TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guide (Rev. B) Nov. 11, 2008
More literature DaVinci Technology Overview Brochure (Rev. B) Sep. 27, 2008
More literature End-to-end video infrastructure solutions Aug. 29, 2008
Application notes Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) Aug. 21, 2008
Application notes Migrating from TMS320DM642 to TMS320DM648/DM6437 Aug. 19, 2008
Application notes Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) Jul. 17, 2008
User guides TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (Rev. B) Feb. 16, 2008
User guides TMS320DM647/DM648 DSP Enhanced DMA (EDMA3) Controller User's Guide (Rev. B) Dec. 08, 2007
User guides TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide (Rev. A) Oct. 02, 2007
User guides TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide (Rev. B) Oct. 02, 2007
User guides TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide (Rev. A) Oct. 02, 2007
User guides TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. B) Oct. 02, 2007
User guides TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide (Rev. A) Oct. 02, 2007
User guides TMS320DM647/DM648 DSP Serial Peripheral Interface (SPI) User’s Guide (Rev. A) Oct. 02, 2007
User guides TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) Oct. 02, 2007
More literature DaVinci Newsletter - Fall 2007 Issue (Rev. B) Aug. 14, 2007
User guides MPEG2 Main Profile Decoder on C64x+ (on DRA446 –Low Memory configuration) UG Jul. 31, 2007
Application notes Migrating from TMS320DM642/3/1/0 to the TMS320DM648/7 Jun. 07, 2007
User guides TMS320DM647/DM648 DSP VLYNQ Port User's Guide Jun. 05, 2007
Application notes Thermal Considerations for the DM64xx, DM64x, and C6000 Devices May 20, 2007

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

APPLICATION SOFTWARE & FRAMEWORKS Download
Multimedia Framework Products (MFP) - Codec Engine, Framework Components and XDAIS
TMDMFP Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Features

Multimedia Framework Products MFP


MFP is completely open source.  It is distributed under the BSD license (with the exception of kernel mode Linux drivers in the Linux Utils product, which are licensed under GPLv2), and is freely available from TI.

  • XDAIS
    TI's well-proven eXpressDSP Algorithm (...)
DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
295
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

995
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

1495
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TI-RTOS Networking
NDKTCPIP TI-RTOS Networking (formerly known as the NDK or Network Developers Kit) combines dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCUs as a part of TI-RTOS and also for TMS320C6000(TM) High Performance DSP-based devices. 
Features

TI-RTOS Networking includes:

  • Core TCP/IP protocol stack: Dual-mode IPv6/IPv4 stack in both source and binary only including VLAN packet priority marking, TCP, UDP, ICMP, IGMP, IP, and ARP
  • Network applications: HTTP, TELNET, TFTP, DNS, DHCP (IPv4 only) in both source and binary form
  • Serial support: PPP (...)
DRIVERS & LIBRARIES Download
TMS320C5000/6000 Image Library (IMGLIB)
SPRC264 C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Image Analysis

  • Image boundry and perimeter
  • Morphological operation
  • Edge detection
  • Image Histogram
  • Image thresholding

Image filtering and format conversion

  • Color space conversion
  • Image convolution
  • Image correlation
  • Error diffusion
  • Median filtering
  • Pixel expansion

Image compression and decompression

  • Forward and (...)
DRIVERS & LIBRARIES Download
C64x+ IQMath Library - A Virtual Floating Point Engine
SPRC542 Texas Instruments TMS320C64x+ IQmath Library is collection of highly optimized and high precision mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed point code on TMS320C64x+ devices. These routines are typically used in computationally (...)
DRIVERS & LIBRARIES Download
Video Imaging Co-Processor (VICP) Signal Processing Library
SPRC831 Texas Instruments VICP Signal processing library is a collection of highly tuned SW algorithms that execute on the VICP H/W accelerator. The library allows the application developer to effectively utilize the VICP performance without spending significant time in developing software for the (...)
Features
Download: VICP Signal Processing Library Archive
Version Windows Download Linux Download
v3.2.0 SPRC831e.zip SPRC847e.gz
v3.1.0 SPRC831d.zip SPRC847d.gz
v3.0.0 SPRC831c.zip SPRC847c.gz
v2.0.2 SPRC831b.zip SPRC847b.gz
v2.0.1 SPRC831a.zip SPRC847a.gz
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
SOFTWARE CODECS Download
CODECS - For DM648 Devices (XDM v0.9)
DM648CODECS TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into your application. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on that page, as (...)
Features

DM648 Codecs are optimized for use on TMS320DM648(tm) devices only. If you seek additional TI codecs, find those optimized for TI C64x+ core-based devices (i.e. most devices in the OMAP35x, C645x, C647x, DM646x, DM644x and DM643x families). For all additional TI codecs, go to Codecs Current (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM256A.ZIP (11 KB) - BSDL Model
SIMULATION MODELS Download
SPRM257A.ZIP (886 KB) - IBIS Model
SIMULATION MODELS Download
SPRM361.ZIP (11 KB) - BSDL Model
SCHEMATICS Download
SLVR328A.PDF (938 KB)
SCHEMATICS Download
SLVR329A.PDF (932 KB)

CAD/CAE symbols

Package Pins Download
(CUT) 529 View options
FCBGA (ZUT) 529 View options

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