NEU

LMK5C23208A

Name: LMK5C23208A
Brand: TI
SKU: LMK5C23208A
Price: 20 USD

AKTIV

Netzwerk-Synchronisierer mit zwei DPLL, drei APLL, zwei Eingängen und acht Ausgängen mit JESD204B/C

Jetzt bestellen

Datenblatt

document-pdfAcrobat LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications datasheet (Englisch) PDF | HTML

LMK5C23208A

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Function

Clock network synchronizer

Number of outputs

8

Output type

CML, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

50

Features

JESD204B

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

3000

Input type

HCSL, LVCMOS, LVDS, LVPECL, XTAL

Supply voltage (min) (V)

3.135

Supply voltage (max) (V)

3.465

Operating temperature range (°C)

-40 to 85

Number of input channels

2

Function

Clock network synchronizer

Number of outputs

8

Output type

CML, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

50

Features

JESD204B

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

3000

Input type

HCSL, LVCMOS, LVDS, LVPECL, XTAL

Supply voltage (min) (V)

3.135

Supply voltage (max) (V)

3.465

Operating temperature range (°C)

-40 to 85

Number of input channels

2

VQFN (RGC)

64

81 mm² 9 x 9

Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks
- 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
- 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
- < 1ppt DCO frequency adjustment step size
2 differential or single-ended DPLL inputs
- 1Hz (1PPS) to 800MHz input frequency
- Digital Holdover and Hitless Switching
8 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
- Up to 12 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1, and GPIO2 and 6 differential outputs on OUT3_P/N to OUT15_P/N
- 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
I2C or 3-wire/4-wire SPI

Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks
- 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
- 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
- < 1ppt DCO frequency adjustment step size
2 differential or single-ended DPLL inputs
- 1Hz (1PPS) to 800MHz input frequency
- Digital Holdover and Hitless Switching
8 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
- Up to 12 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1, and GPIO2 and 6 differential outputs on OUT3_P/N to OUT15_P/N
- 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
I2C or 3-wire/4-wire SPI

The LMK5C23208A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates two DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5C23208A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates two DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

filter

Andere Netzwerk-Taktsynchronisierer suchen

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star

=Von TI ausgewählte Top-Empfehlungen für dieses Produkt

Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.

Alle anzeigen 4

	Typ	Titel		Datum
*	Data sheet	LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications datasheet	PDF \| HTML	14 Mai 2025
	Application note	Termination Guidelines for Differential and Single-Ended Signals	PDF \| HTML	10 Dez 2025
	User guide	LMK5C23208A Programmer's Guide (Rev. A)	PDF \| HTML	17 Nov 2025
	Application note	Oscillator Power Considerations for PLL Devices	PDF \| HTML	30 Okt 2025

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)

Anfordern

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
VQFN (RGC)	64	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

LMK5C23208A

Netzwerk-Synchronisierer mit zwei DPLL, drei APLL, zwei Eingängen und acht Ausgängen mit JESD204B/C

LMK5C23208A

Produktdetails

Technische Dokumentation

Design und Entwicklung

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

Bestellen & Qualität

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Videoreihe

Videos