(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
(2) The device is available with Q100 qualification as the SN65HVD1050Q (Product Preview).
(3) The signaling rate of a line is the number of voltage transitions that are made, per second, expressed in the units bps (bits per second).
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The SN65HVD1050 meets or exceeds the specifications of the ISO 11898 standard for use in applications employing a controller area network (CAN). The device is also qualified for use in automotive applications in accordance with AEC-Q100.(2)
As a CAN transceiver, this device provides differential transmit capability to the bus and differential receive capability to a CAN controller at signaling rates up to 1 megabit per second (Mbps)(3).
Designed for operation in especially harsh environments, the SN65HVD1050 features
cross-wire, overvoltage, and loss of ground protection from –27 V to 40 V, overtemperature protection, a –12-V to 12-V common-mode range, and withstands
voltage transients from
–200 V to 200 V, according to ISO 7637.
Pin 8 provides for two different modes of operation: high-speed or silent mode. The high-speed mode of operation is selected by connecting S (pin 8) to ground.
If a high logic level is applied to the S pin of the SN65HVD1050, the device enters a listen-only silent mode, during which the driver is switched off while the receiver remains fully functional.
In silent mode, all bus activity is passed by the receiver output to the local protocol controller. When data transmission is required, the local protocol controller reverses this low-current silent mode by placing a logic low on the S pin to resume full operation.
A dominant-time-out circuit in the SN65HVD1050 prevents the driver from blocking network communication with a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the next rising edge on TXD.
Vref (pin 5) is available as a VCC/2 voltage reference.
The SN65HVD1050M is characterized for operation from –55°C to 125°C.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | SN65HVD1050-EP datasheet (Rev. A) | 22 Okt 2009 | |
| * | VID | SN65HVD1050-EP VID V6207608 | 21 Jun 2016 | |
| * | Radiation & reliability report | SN65HVD1050MDREP Reliability Report | 26 Okt 2011 |
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| Gehäuse | Pins | Herunterladen |
|---|---|---|
| SOIC (D) | 8 | Optionen anzeigen |
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