ADS4249

ACTIVO

Convertidor analógico a digital (ADC) de dos canales, 14 bits y 250 MSPS

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Funcionalidad similar a la del dispositivo comparado
ADC3648 ACTIVO ADC de 14 bits, 2 canales y 250 MSPS con interfaz LVDS y decimación de hasta 32768x Higher SNR

Detalles del producto

Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 600 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 470 Architecture Pipeline SNR (dB) 72.8 ENOB (Bits) 11.45 SFDR (dB) 82 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 600 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 470 Architecture Pipeline SNR (dB) 72.8 ENOB (Bits) 11.45 SFDR (dB) 82 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 250 MSPS
  • Ultra-Low Power with Single 1.8-V Supply:
    • 560-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80-dBc SFDR at 170 MHz
    • 71.7-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with
      Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
    Lead (QFN) Package
  • Maximum Sample Rate: 250 MSPS
  • Ultra-Low Power with Single 1.8-V Supply:
    • 560-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80-dBc SFDR at 170 MHz
    • 71.7-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with
      Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
    Lead (QFN) Package

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

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Pin por pin con la misma funcionalidad que el dispositivo comparado
ADS4229 ACTIVO Convertidor analógico a digital (ADC) de dos canales, 12 bits y 250 MSPS Same family, pinout and speed, but 12-bit resolution.

Documentación técnica

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Documentación principal Tipo Título Opciones de formato Fecha
* Data sheet ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC datasheet (Rev. E) PDF | HTML 07 ene 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 may 2015
Application note Signal Chain Noise Figure Analysis 29 oct 2014
Design guide TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide 03 sep 2013
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 jul 2013
User guide TIDA-00070 Verified Design Reference Guide 23 ene 2013
User guide HSDC-SEK-10 17 ene 2013
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 jul 2012
Application note High-Speed, Analog-to-Digital Converter Basics 11 ene 2012
User guide TSW3725 Evaluation Module 25 oct 2011
Application note QFN Layout Guidelines 28 jul 2006

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADS4249EVM — Módulo de evaluación del convertidor analógico a digital ADS4249 de dos canales, 14 bits y 250 MSPS

The ADS4249EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4249 device, an extremely low power dual channel 14-bit 250 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a (...)

Guía del usuario: PDF
Placa de evaluación

TSW1265EVM — Plataforma de diseño y evaluación de referencia de receptor doble de banda ancha

The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)

Guía del usuario: PDF
GUI para el módulo de evaluación (EVM)

ADS58C28SPIGUI-SW ADS42xxx SPI GUI

ADS58C28SPIGUI-SW is the installation package for ADS58C28_ADS42xx_GUI which is used to access or write internal registers of ADS58C28 through an on-board USB port.
Productos y hardware compatibles

Productos y hardware compatibles

GUI para el módulo de evaluación (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Productos y hardware compatibles

Productos y hardware compatibles

Modelo de simulación

ADS4249 IBIS Model

SBAM107.ZIP (41 KB) - IBIS Model
Herramienta de cálculo

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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Productos y hardware compatibles

Herramienta de diseño

SBAC119 TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Productos y hardware compatibles

Productos y hardware compatibles

Esquema

ADS42XX_58C28EVM DesignPkg (Rev. B)

SLAC459B.ZIP (6548 KB)
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® para TI es un entorno de diseño y simulación que ayuda a evaluar la funcionalidad de los circuitos analógicos. Esta completa suite de diseño y simulación utiliza un motor de análisis analógico de Cadence®. Disponible sin ningún costo, PSpice para TI incluye una de las bibliotecas de modelos (...)
Diseños de referencia

TIDA-00073 — Diseño de receptor RF a digital de doble banda ancha

The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this.  This reference EVEM coupled with a capture (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00070 — Proyecto de firmware FPGA para medir errores de bits en el canal de salida de un convertidor A a D.

For applications where there are bit errors and resulting sample errors (also called sparkle codes, word errors, or code errors), the ability to measure the Error rates caused by these bit errors is important. This FPGA firmware based application note proposes a method to accurately measure these (...)
Guía del usuario: PDF
Esquema: PDF
Diseños de referencia

TIDA-00069 — Ejemplo de FPGA Firmware de cómo conectar FPGA Altera a convertidores de datos de interfaz LVDS de a

This reference design and the associated example Verilog code can be used as a starting point for interfacing Altera FPGAs to Texas Instruments' high-speed LVDS-interface analog-to-digital converters (ADC) and digital-to-analog converters (DAC). The firmware implementation is explained and the (...)
Guía del usuario: PDF
Esquema: PDF
Diseños de referencia

TIDA-00068 — Transceptor de estación base con ruta de retroalimentación DPD

The design is for a small cell base station development platform.  It provides two real receive paths, two complex transmit paths, and a shared real feedback path.  This design has macro basestation performance, but with small cell base station footprint.  The current design handles (...)
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
VQFN (RGC) 64 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL)/reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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