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CDCV855

新規設計での使用を推奨しません

1:4、DDR、PLL クロック ドライバ

ご注文はこちら
データシート
CDCV855 は新規設計での使用を推奨しません
これまでにご購入されたお客様をサポートする目的でこの製品を引き続き生産しています。新規設計では代替品をご検討ください。
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CDCVF855 アクティブ 2.5V フェーズ・ロック・ループ・クロック・ドライバ Can achieve wider frequency ranges

CDCV855

新規設計での使用を推奨しません
データシート ご注文はこちら

製品詳細

Core supply voltage (V) 2.5 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog
Core supply voltage (V) 2.5 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog
  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 MHz to 180 MHz
  • Low Jitter (cyc–cyc): ±50 ps
  • Distributes One Differential Clock Input to Four Differential Clock Outputs
  • Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low
  • Operates From Dual 2.5-V Supplies
  • 28-Pin TSSOP Package
  • Consumes < 200-µA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks
  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 MHz to 180 MHz
  • Low Jitter (cyc–cyc): ±50 ps
  • Distributes One Differential Clock Input to Four Differential Clock Outputs
  • Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low
  • Operates From Dual 2.5-V Supplies
  • 28-Pin TSSOP Package
  • Consumes < 200-µA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to four differential pairs of clock outputs (Y[0:3], Y[0:3]\) and one differential pair of feedback clock outputs (FBOUT, FBOUT\). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV855 is characterized for both commercial and industrial temperature ranges.

The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to four differential pairs of clock outputs (Y[0:3], Y[0:3]\) and one differential pair of feedback clock outputs (FBOUT, FBOUT\). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV855 is characterized for both commercial and industrial temperature ranges.
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート 2.5-V Phase-Lock Loop Clock Driver データシート (Rev. A) 2002年 12月 12日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点