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CDCVF2505-Q1

新規設計での使用を推奨しません

同期、DRAM、汎用アプリケーション向け、スペクトラム拡散互換車載 PLL クロック・ドライバ

ご注文はこちら
データシート
CDCVF2505-Q1 は新規設計での使用を推奨しません
これまでにご購入されたお客様をサポートする目的でこの製品を引き続き生産しています。新規設計では代替品をご検討ください。
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比較対象デバイスと類似の機能
CDCVF2505 アクティブ PLL クロック・ドライバ。用途は SDRAM と汎用アプリケーション、スペクトラム拡散との互換性確保、パワーダウン・モード搭載 Can achieve better performance

CDCVF2505-Q1

新規設計での使用を推奨しません
データシート ご注文はこちら

製品詳細

Function Memory interface Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 200 Number of outputs 4 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 150 Operating temperature range (°C) -40 to 85 Rating Automotive
Function Memory interface Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 200 Number of outputs 4 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 150 Operating temperature range (°C) -40 to 85 Rating Automotive
  • Qualified for Automotive Applications
  • Phase-Locked Loop Clock Driver for Synchronous DRAM
    and General-Purpose Applications
  • Spread-Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-to-Cycle): <150 ps Over the
    Range 66 MHz to 200 MHz
  • Distributes One Clock Input to One Bank of Five Outputs
    (CLKOUT Is Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is No Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin SOIC Package
  • Consumes Less Than 100 µA (Typically) in
    Power Down Mode
  • Internal Feedback Loop Is Used to Synchronize the
    Outputs to the Input Clock
  • 25- On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the
    Need for External Components
  • Qualified for Automotive Applications
  • Phase-Locked Loop Clock Driver for Synchronous DRAM
    and General-Purpose Applications
  • Spread-Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-to-Cycle): <150 ps Over the
    Range 66 MHz to 200 MHz
  • Distributes One Clock Input to One Bank of Five Outputs
    (CLKOUT Is Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is No Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin SOIC Package
  • Consumes Less Than 100 µA (Typically) in
    Power Down Mode
  • Internal Feedback Loop Is Used to Synchronize the
    Outputs to the Input Clock
  • 25- On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the
    Need for External Components

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.

Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.

Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

The CDCVF2505 is characterized for operation from –40°C to 85°C.
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート 3.3-V Clock Phase-Locked Loop Clock Driver データシート 2008年 11月 21日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点