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DS90LV001

アクティブ

800Mbps LVDS バッファ

製品詳細

Function Buffer Protocols LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 800 Input signal LVCMOS, LVDS, LVPECL, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer Protocols LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 800 Input signal LVCMOS, LVDS, LVPECL, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) WSON (NGK) 8 9 mm² (3 mm × 3 mm)
  • Single +3.3 V Supply
  • LVDS Receiver Inputs Accept LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (Typ)
  • Low Jitter 800 Mbps Fully Differential Data Path
  • 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • 8 pin SOIC and Space Saving (70%) WSON Package
  • Industrial Temperature Range

All trademarks are the property of their respective owners.

  • Single +3.3 V Supply
  • LVDS Receiver Inputs Accept LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (Typ)
  • Low Jitter 800 Mbps Fully Differential Data Path
  • 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • 8 pin SOIC and Space Saving (70%) WSON Package
  • Industrial Temperature Range

All trademarks are the property of their respective owners.

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC.

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC.

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技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート DS90LV001 800 Mbps LVDS Buffer データシート (Rev. E) 2013/04/22
アプリケーション概要 How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver 2019/01/09
アプリケーション・ノート Signaling Rate vs. Distance for Differential Buffers 2010/01/26
ホワイト・ペーパー Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches 2001/08/01
アプリケーション・ノート LVDS技術の概要 英語版 1998/10/05

設計と開発

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シミュレーション・モデル

DS90LV001 IBIS Model

SNLM045.ZIP (29 KB) - IBIS モデル
サポート対象の製品とハードウェア
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
SOIC (D) 8 Ultra Librarian
WSON (NGK) 8 Ultra Librarian

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