SN74ABT18640
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Members of the Texas Instruments WidebusTM Family
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat
(WD) Packages
SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.
The 'ABT18640 scan test devices with 18-bit inverting bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers.
Data flow is controlled by the direction-control (DIR) and
output-enable (
) inputs. Data
transmission is allowed from the A bus to the B bus or from the B bus
to the A bus, depending on the logic level at DIR. can be used to disable the device
so that the buses are effectively isolated.
In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN74ABT18640 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT18640 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18640 is characterized for operation from -40°C to 85°C.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | Scan Test Devices With 18-Bit Inverting Bus Transceivers データシート (Rev. C) | 1996/07/01 | |||
| アプリケーション・ノート | Programming CPLDs Via the 'LVT8986 LASP | 2005/11/01 | ||||
| EVM ユーザー ガイド (英語) | LASP Demo Board User's Guide | 2005/11/01 |
設計と開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| SSOP (DL) | 56 | Ultra Librarian |