TMS320DM6467

アクティブ

デジタル メディア システムオンチップ

製品詳細

DSP type 1 C64x DSP (max) (MHz) 594, 729 CPU 32-/64-bit Operating system DSP/BIOS, Linux, VLX Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 594, 729 CPU 32-/64-bit Operating system DSP/BIOS, Linux, VLX Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (CUT) 529 361 mm² 19 x 19
  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 594-, 729-MHz C64x+™ Clock Rate
    • 297-, 364.5-MHz ARM926EJ-Strade; Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752, 5832 C64x+ MIPS
    • Fully Software-Compatible With C64x/ARM9™
    • Supports SmartReflex™ [-594 only]
      • Class 0
      • 1.05-V and 1.2-V Adaptive Core Voltage
    • Extended Temp Available [-594 only]
    • Industrial Temp Available [-729 only]
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 ×: 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 32K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines
    • Supports a Range of Encode, Decode, and Transcode Operations
      • H.264, MPEG2, VC1, MPEG4 SP/ASP
  • Video Port Interface (VPIF)
    • Two 8-Bit SD (BT.656), Single 16-Bit HD (BT.1120), or Single Raw (8-/10-/12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656) or Single 16-Bit HD (BT.1120) Video Display Channels
  • Video Data Conversion Engine (VDCE)
    • Horizontal and Vertical Downscaling
    • Chroma Conversion (4:2:2↔4:2:0)
  • Two Transport Stream Interface (TSIF) Modules
    (One Parallel/Serial and One Serial Only)
    • TSIF for MPEG Transport Stream
    • Simultaneous Synchronous or Asynchronous Input/Output Streams
    • Absolute Time Stamp Detection
    • PID Filter With 7 PID Filter Tables
    • Corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery
  • External Memory Interfaces (EMIFs)
    • 297-.310.5-MHz 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
    • Programmable Default Burst Size
  • 10/100/1000 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • Supports MII and GMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • 32-Bit, 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
    • Conforms to PCI Specification 2.3
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watchdog Timer
  • Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals)
    • Supports up to 1.8432 Mbps UART
    • SIR and MIR (0.576 MBAUD)
    • CIR With Programmable Data Encoding
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Multichannel Audio Serial Ports (McASPs)
    • One Four-Serializer Transmit/Receive Port
    • One Single DIT Transmit Port for S/PDIF
  • 32-Bit Host Port Interface (HPI)
  • VLYNQ™ Interface (FPGA Interface)
  • Two Pulse Width Modulator (PWM) Outputs
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Up to 33 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • On-Chip ARM ROM Bootloader (RBL)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 529-Pin Pb-Free BGA Package (CUT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2/1.05-V Internal

All trademarks are the property of their respective owners.

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 594-, 729-MHz C64x+™ Clock Rate
    • 297-, 364.5-MHz ARM926EJ-Strade; Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752, 5832 C64x+ MIPS
    • Fully Software-Compatible With C64x/ARM9™
    • Supports SmartReflex™ [-594 only]
      • Class 0
      • 1.05-V and 1.2-V Adaptive Core Voltage
    • Extended Temp Available [-594 only]
    • Industrial Temp Available [-729 only]
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 ×: 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 32K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines
    • Supports a Range of Encode, Decode, and Transcode Operations
      • H.264, MPEG2, VC1, MPEG4 SP/ASP
  • Video Port Interface (VPIF)
    • Two 8-Bit SD (BT.656), Single 16-Bit HD (BT.1120), or Single Raw (8-/10-/12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656) or Single 16-Bit HD (BT.1120) Video Display Channels
  • Video Data Conversion Engine (VDCE)
    • Horizontal and Vertical Downscaling
    • Chroma Conversion (4:2:2↔4:2:0)
  • Two Transport Stream Interface (TSIF) Modules
    (One Parallel/Serial and One Serial Only)
    • TSIF for MPEG Transport Stream
    • Simultaneous Synchronous or Asynchronous Input/Output Streams
    • Absolute Time Stamp Detection
    • PID Filter With 7 PID Filter Tables
    • Corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery
  • External Memory Interfaces (EMIFs)
    • 297-.310.5-MHz 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
    • Programmable Default Burst Size
  • 10/100/1000 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • Supports MII and GMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • 32-Bit, 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
    • Conforms to PCI Specification 2.3
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watchdog Timer
  • Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals)
    • Supports up to 1.8432 Mbps UART
    • SIR and MIR (0.576 MBAUD)
    • CIR With Programmable Data Encoding
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Multichannel Audio Serial Ports (McASPs)
    • One Four-Serializer Transmit/Receive Port
    • One Single DIT Transmit Port for S/PDIF
  • 32-Bit Host Port Interface (HPI)
  • VLYNQ™ Interface (FPGA Interface)
  • Two Pulse Width Modulator (PWM) Outputs
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Up to 33 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • On-Chip ARM ROM Bootloader (RBL)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 529-Pin Pb-Free BGA Package (CUT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2/1.05-V Internal

All trademarks are the property of their respective owners.

The TMS320DM6467 (also referenced as DM6467) leverages TI's DaVinci™ technology to meet the networked media encode and decode digital media processing needs of next-generation embedded devices.

The DM6467 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6467 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 5832 million instructions per second (MIPS) at a clock rate of 729 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(literature number SPRU732).

The DM6467 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6467 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a configurable video port; a 10/100/1000 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; a 4-bit transfer/4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel audio serial port (McASP0) with 4 serializers; a secondary multichannel audio serial port (McASP1) with a single transmit serializer; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a configurable 32-bit host port interface (HPI); up to 33-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART/IrDA/CIR interfaces with modem interface signals on UART0; 2 pulse width modulator (PWM) peripherals; an ATA/ATAPI-6 interface; a 33-MHz peripheral component interface (PCI); and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6467 and the network. The DM6467 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode; and 1000Base-TX (1 Gbps) in full-duplex mode with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The PCI, HPI, I2C, SPI, USB2.0, and VLYNQ ports allow the DM6467 to easily control peripheral devices and/or communicate with host processors.

The DM6467 also includes a High-Definition Video/Imaging Co-processor (HDVICP) and Video Data Conversion Engine (VDCE) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the HDVICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6467 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320DM6467 (also referenced as DM6467) leverages TI's DaVinci™ technology to meet the networked media encode and decode digital media processing needs of next-generation embedded devices.

The DM6467 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6467 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 5832 million instructions per second (MIPS) at a clock rate of 729 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(literature number SPRU732).

The DM6467 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6467 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a configurable video port; a 10/100/1000 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; a 4-bit transfer/4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel audio serial port (McASP0) with 4 serializers; a secondary multichannel audio serial port (McASP1) with a single transmit serializer; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a configurable 32-bit host port interface (HPI); up to 33-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART/IrDA/CIR interfaces with modem interface signals on UART0; 2 pulse width modulator (PWM) peripherals; an ATA/ATAPI-6 interface; a 33-MHz peripheral component interface (PCI); and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6467 and the network. The DM6467 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode; and 1000Base-TX (1 Gbps) in full-duplex mode with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The PCI, HPI, I2C, SPI, USB2.0, and VLYNQ ports allow the DM6467 to easily control peripheral devices and/or communicate with host processors.

The DM6467 also includes a High-Definition Video/Imaging Co-processor (HDVICP) and Video Data Conversion Engine (VDCE) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the HDVICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6467 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート TMS320DM6467 Digital Media System-on-Chip データシート (Rev. H) 2012年 7月 11日
* エラッタ TMS320DM6467 DMSoC Silicon Errata Silicon Revisions 3.0, 1.1, and 1.0 (Rev. G) 2010年 11月 2日
アプリケーション・ノート High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
アプリケーション・ノート Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
ユーザー・ガイド TMS320DM646x DMSoC Inter-Integrated Circuit (I2C) Module User's Guide (Rev. D) 2011年 3月 25日
ユーザー・ガイド TMS320DM646x DMSoC DDR2 Memory Controller User's Guide (Rev. E) 2011年 3月 21日
ユーザー・ガイド TMS320DM646x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. B) 2011年 3月 17日
アプリケーション・ノート Using the TMS320DM646x DMSoC Bootloader (Rev. D) 2011年 3月 4日
ユーザー・ガイド TMS320DM646x DMSoC Enhanced Direct Memory Access Controller (EDMA) User's Guide (Rev. B) 2011年 1月 14日
ユーザー・ガイド TMS320DM646x DMSoC 64-Bit Timer User's Guide (Rev. B) 2011年 1月 7日
ユーザー・ガイド TMS320DM646x DMSoC EMAC/MDIO Module User's Guide (Rev. A) 2010年 12月 23日
ユーザー・ガイド TMS320DM646x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. A) 2010年 8月 6日
ユーザー・ガイド TMS320DM646x DMSoC ARM Subsystem Reference Guide (Rev. E) 2010年 8月 4日
ユーザー・ガイド TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 2010年 8月 3日
ユーザー・ガイド TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010年 7月 30日
アプリケーション・ノート Migrating from TMS320DM6467 to TMS320DM6467T (Rev. B) 2010年 6月 8日
アプリケーション・ノート Using the Video Port of TMS320DM646x (Rev. A) 2010年 4月 6日
アプリケーション・ノート USB Compliance Checklist (Rev. A) 2010年 3月 10日
ユーザー・ガイド TMS320DM646x DMSoC Universal Serial Bus (USB) Controller User's Guide (Rev. E) 2009年 11月 20日
ユーザー・ガイド TMS320DM646x DMSoC Peripheral Component Interconnect (PCI) User's Guide (Rev. B) 2009年 11月 16日
ユーザー・ガイド TMS320DM646x DMSoC Peripherals Overview Reference Guide (Rev. B) 2009年 11月 16日
ユーザー・ガイド TMS320DM646x DMSoC Video Port Interface (VPIF) User's Guide (Rev. D) 2009年 11月 16日
アプリケーション・ノート TMS320DM6467 Power Consumption Summary (Rev. B) 2009年 10月 24日
アプリケーション・ノート Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms 2009年 9月 24日
ユーザー・ガイド TMS320DM646x DMSoC Video Data Conversion Engine (VDCE) User's Guide (Rev. A) 2009年 8月 26日
ユーザー・ガイド TMS320DM646x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. C) 2009年 7月 14日
アプリケーション・ノート LSP 2.10 DaVinci Linux Drivers (Rev. A) 2009年 7月 8日
ユーザー・ガイド TMS320DM646x DMSoC Universal Asynchronous Receiver/Transmitter (UART) User's Gde (Rev. D) 2009年 6月 21日
アプリケーション・ノート TMS320DM6467 SoC Architecture and Throughput Overview (Rev. B) 2009年 6月 10日
ユーザー・ガイド TMS320DM646x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 2009年 3月 13日
ユーザー・ガイド TMS320C64x+ DSP Cache User's Guide (Rev. B) 2009年 2月 11日
アプリケーション・ノート Multiple TMS320DM6467 PCI Interface 2009年 2月 10日
アプリケーション・ノート PCI Express to TMS320DM646x PCI Interface Through XIO2000A Bridge 2009年 2月 3日
ユーザー・ガイド TMS320DM646x DMSoC ATA Controller User's Guide (Rev. A) 2009年 1月 27日
ユーザー・ガイド TMS320DM6467 DVEVM v2.0 Getting Started Guide (Rev. D) 2008年 12月 31日
アプリケーション・ノート Migrating from TMS320DM642 to TMS320DM6467 2008年 11月 17日
アプリケーション・ノート Migrating from TMS320DM6446 to TMS320DM6467 2008年 11月 17日
製品概要 TMS320C6000 高性能 DSP シリーズ プロダクト・ブリテン (Rev. B 翻訳版) 2008年 11月 17日
ユーザー・ガイド TMS320DM646x DMSoC Host Port Interface (HPI) User's Guide (Rev. A) 2008年 11月 7日
その他の技術資料 DaVinci Technology Overview Brochure (Rev. B) 2008年 9月 27日
アプリケーション・ノート Enabling SmartReflex on the TMS320DM6467 2008年 9月 10日
その他の技術資料 End-to-end video infrastructure solutions 2008年 8月 29日
アプリケーション・ノート Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日
ユーザー・ガイド TMS320DM646x DMSoC Transport Stream Interface (TSIF) Module User's Guide (Rev. E) 2008年 7月 2日
アプリケーション・ノート TMS320DM6467 Universal Serial Bus Downstream Host Compliance Testing 2008年 5月 30日
アプリケーション・ノート Building a Small Embedded Linux Kernel Example (Rev. A) 2008年 5月 27日
アプリケーション・ノート HDMI Transmitter/Receiver Support on TMS320DM6467 2008年 5月 5日
アプリケーション・ノート TMS320DM64xx、TMS320DM64x、および TMS320C6000 デバイスにおける熱考察 英語版 2008年 5月 5日
ユーザー・ガイド TMS320DM646x DMSoC Multichannel Audio Serial Port (McASP) User's Guide (Rev. B) 2008年 3月 13日
アプリケーション・ノート TMS320DM6467 Universal Serial Bus Upstream Device Compliance Testing 2008年 1月 30日
その他の技術資料 DaVinci Newsletter 4Q 2007 - DM6467 Issue 2007年 12月 3日
その他の技術資料 TMS320DM6467 DaVinci FAQ 2007年 12月 3日
ユーザー・ガイド TMS320DM646x DMSoC Clock Reference Generator (CRGEN) User's Guide 2007年 12月 3日
ユーザー・ガイド TMS320DM646x DMSoC DSP Subsystem Reference Guide 2007年 12月 3日
ユーザー・ガイド TMS320DM646x DMSoC VLYNQ Port User's Guide 2007年 12月 3日
アプリケーション・ノート Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005年 10月 20日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

デバッグ・プローブ

TMDSEMU200-U — XDS200 USB デバッグ・プローブ

XDS200 は、TI の組込みデバイスのデバッグに使用できるデバッグ・プローブ (エミュレータ) です。XDS200 は、低コストの XDS110 と高性能の XDS560v2 に比べて、低コストと良好な性能のバランスを特長としています。単一のポッド (筐体) で、多様な規格 (IEEE1149.1、IEEE1149.7、SWD) をサポートします。すべての XDS デバッグ・プローブは、組込みトレース・バッファ (ETB) を搭載しているすべての Arm® プロセッサと DSP プロセッサで、コア・トレースとシステム・トレースをサポートしています。ピン経由でコア・トレースを実行する場合、 (...)

デバッグ・プローブ

TMDSEMU560V2STM-U — XDS560™ ソフトウェア v2 システム・トレース USB デバッグ・プローブ

XDS560v2 は、XDS560™ ファミリのデバッグ・プローブの中で最高の性能を達成し、従来の JTAG 規格 (IEEE1149.1) と cJTAG (IEEE1149.7) の両方をサポートしています。シリアル・ワイヤ・デバッグ (SWD) をサポートしていないことに注意してください。

すべての XDS デバッグ・プローブは、組み込みトレース・バッファ (ETB) を搭載しているすべての ARM プロセッサと DSP プロセッサで、コア・トレースとシステム・トレースをサポートしています。ピン経由でコア・トレースを実行する場合、XDS560v2 PRO TRACE が必要です。

(...)

デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

ソフトウェア開発キット (SDK)

LINUXDVSDK-DV — Linux デジタル・ビデオ・ソフトウェア開発キット(DVSDK)v2x/v3x - DaVinci デジタル・メディア・プロセッサ

発効日:2010 年 10 月 - Linux DVSDK v4 のリリース日。 上記に掲載されていない各種 DaVinci™ デバイスについては、ご希望のデバイスの型番を TIウェブサイトで検索してください。今後、この製品ページに、お客様がご使用になっている最新の DVSDK へのリンクを掲載する予定です。

DaVinci システムのインテグレータの皆様は、Linux™ デジタル・ビデオ・ソフトウェア開発キット (DVSDK) を使用すると、Linux ベースのマルチメディア・アプリケーションを迅速に開発し、DaVinci (...)

アプリケーション・ソフトウェアとフレームワーク

TMDMFP — マルチメディア・フレームワーク製品(MFP)- コーデック・エンジン、フレームワーク・コンポーネントおよび XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable DSPs over fixed-function devices is their ability to accelerate multiple multimedia functions in a single device. TI multimedia framework products are designed to enable users to easily share a DSP between algorithms by handling (...)

ユーザー ガイド: PDF
サンプル・コードまたはデモ

DEMOAPP-DM6467 — デモ版 - DM6467 サンプル・アプリケーションおよびデモ・コード

Free Example Code - TI provides proof-of-concept application code to demonstrate some of the hardware and software capabilities of its devices.

  • Click GET SOFTWARE to access Application Demo and Documentation, based on the DM6467 EVM (evaluation module).
ソフトウェア・コーデック

C64XPLUSCODECS — CODECS - ビデオおよびスピーチ C64x+-ベース・デバイス (OMAP35x、C645x、C647x、DM646、DM644x、DM643x)

TI のコーデックは無償であり、量産ライセンスが付属しているほか、今すぐダウンロードできます。いずれも量産テスト済みで、ビデオや音声の各アプリケーションに簡単に統合可能です。(上にある) 「GET SOFTWARE」 (ソフトウェアを入手) ボタンをクリックすると、最新のテスト済みコーデック・バージョンを入手できます。各インストーラやダウンロード・ページから、データシートとリリース・ノートが利用可能です。

 

追加情報:

ソフトウェア・コーデック

DM6467CODECS DM6467 用コーデック - ソフトウェアとドキュメント

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
デジタル信号プロセッサ (DSP)
TMS320DM6467 デジタル メディア システムオンチップ TMS320DM6467T デジタル メディア システムオンチップ
ダウンロードオプション
シミュレーション・モデル

DM646x ZUT BSDL Model (Rev. A)

SPRM276A.ZIP (12 KB) - BSDL Model
シミュレーション・モデル

DM646x ZUT IBIS Model (Rev. E)

SPRM277E.ZIP (753 KB) - IBIS Model
計算ツール

SPRC815 Download: TMS320DM6467 Pin Mux Utility

The DM6467 uses a great deal of internal pin multiplexing to allow the most functionality in the smallest and lowest cost package. This utility allows the pin multiplexing registers of the device to be calculated with ease, as well as showing what peripherals can be used together. This software (...)
サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
デジタル信号プロセッサ (DSP)
TMS320DM6467 デジタル メディア システムオンチップ
回路図

TMS320DM646x Orcad Symbols

SPRR103.ZIP (10 KB)
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
FCBGA (CUT) 529 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

サポートとトレーニング

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コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​

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