DS92LX1621

활성

양방향 제어 채널을 지원하는 10MHz~50MHz DC 밸런싱된 채널 링크 III 시리얼라이저

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document-pdfAcrobat DS92LX1621/1622 10-50MHz DC-Balanced Ch Link III SER/DES w/Bidirectional Ctrl Ch datasheet (Rev. I) (영어)

DS92LX1621

활성

데이터 시트

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Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

WQFN (RTV)

32

25 mm² (5 mm × 5 mm)

Configurable Data Throughput
- 12–bit (min) up to 600 Mbits/sec
- 16–bit (def) up to 800 Mbits/sec
- 18–bit (max) up to 900 Mbits/sec
10 MHz to 50 MHz Input Clock Support
Embedded Clock with DC Balanced Coding to
Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded
Twisted-Pair
Bi-Directional Control Interface Channel with
I²C Support
I²C Interface for Device
Configuration. Single-pin ID Addressing
16–bit Data Payload with CRC (Cyclic
Redundancy Check) for Checking Data Integrity
with Programmable Data Transmission Error
Detection and Interrupt Control
Up to 6 Programmable GPIO’s
AT-SPEED BIST Diagnosis Feature to Validate
Link Integrity
Individual Power-Down Controls for Both SER
and DES
User-Selectable Clock Edge for Parallel Data
on Both SER and DES
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus Interface
Single Power Supply at 1.8V
IEC 61000–4–2 ESD Compliant
No Reference Clock Required on Deserializer
Programmable Receive Equalization
LOCK Output Reporting Pin to Ensure Link
Status
EMI/EMC Mitigation
- DES Programmable Spread Spectrum (SSCG)
  Outputs
- DES Receiver Staggered Outputs
Temperature Range −40°C to +85°C
SER Package: 32 Pin WQFN (5mm × 5mm)
DES Package: 40 Pin WQFN (6mm × 6mm)

Configurable Data Throughput
- 12–bit (min) up to 600 Mbits/sec
- 16–bit (def) up to 800 Mbits/sec
- 18–bit (max) up to 900 Mbits/sec
10 MHz to 50 MHz Input Clock Support
Embedded Clock with DC Balanced Coding to
Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded
Twisted-Pair
Bi-Directional Control Interface Channel with
I²C Support
I²C Interface for Device
Configuration. Single-pin ID Addressing
16–bit Data Payload with CRC (Cyclic
Redundancy Check) for Checking Data Integrity
with Programmable Data Transmission Error
Detection and Interrupt Control
Up to 6 Programmable GPIO’s
AT-SPEED BIST Diagnosis Feature to Validate
Link Integrity
Individual Power-Down Controls for Both SER
and DES
User-Selectable Clock Edge for Parallel Data
on Both SER and DES
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus Interface
Single Power Supply at 1.8V
IEC 61000–4–2 ESD Compliant
No Reference Clock Required on Deserializer
Programmable Receive Equalization
LOCK Output Reporting Pin to Ensure Link
Status
EMI/EMC Mitigation
- DES Programmable Spread Spectrum (SSCG)
  Outputs
- DES Receiver Staggered Outputs
Temperature Range −40°C to +85°C
SER Package: 32 Pin WQFN (5mm × 5mm)
DES Package: 40 Pin WQFN (6mm × 6mm)

The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I²C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.

The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package.

The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I²C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.

The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package.

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5개 모두 보기

상위 문서	유형	직함	날짜
*	데이터 시트	DS92LX1621/1622 10-50MHz DC-Balanced Ch Link III SER/DES w/Bidirectional Ctrl Ch datasheet (Rev. I)	2014. 1. 21
	애플리케이션 노트	High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs	2018. 11. 9
	애플리케이션 노트	DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)	2013. 4. 29
	사용 설명서	LX16EVK01 Channel Link III Ser/Des Evaluation Kit User Guide	2012. 1. 25
	애플리케이션 노트	Go the Distance: Industrial SerDes with Embedded Clock and Control	2010. 10. 20

설계 및 개발

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평가 보드

LX16EVK01 — LX16EVK01 평가 키트

The LX16EVK01 is an evaluation kit designed to demonstrate the performance and capabilities of the DS92LX1621 and DS92LX1622 Channel Link III Serializer/Deserializer chipset.

The DS92LX1621 serializer board accepts LVCMOS input signals for the high speed forward channel and provides additional (...)

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