DS99R103
- 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
- Capable to Drive Shielded Twisted-Pair Cable
- User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
- Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
- Individual Power-Down Controls for both Transmitter and Receiver
- Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
- All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
- LOCK Output Flag to Ensure Data Integrity at Receiver Side
- Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
- PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
- All LVCMOS inputs and control pins have internal pulldown
- On-Chip Filters for PLLs on Transmitter and Receiver
- Integrated 100Ω Input Termination on Receiver
- 4 mA Receiver Output Drive
- 48-Pin TQFP and 48-Pin WQFN Packages
- Pure CMOS .35 μm Process
- Power Supply Range 3.3V ± 10%
- Temperature Range −40°C to +85°C
- 8 kV HBM ESD Tolerance
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The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet (Rev. D) | 2013/04/16 | |
| Application note | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013/04/29 | ||
| Application note | Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) | 2013/04/26 | ||
| User guide | SERDES Demonstration Kit User Manual | 2012/01/25 | ||
| Design guide | Channel Link II Design Guide | 2011/01/21 |
설계 및 개발
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| 패키지 | 핀 | 다운로드 |
|---|---|---|
| TQFP (PFB) | 48 | 옵션 보기 |
| WQFN (NJU) | 48 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치