인터페이스 LVDS, M-LVDS 및 PECL

고속 차동 라인 리시버

SN65LVDT388은(는) 새 설계에 권장하지 않습니다
이 제품은 이전 설계를 지원하기 위해 계속 생산 중이지만 새로운 설계에 사용하는 것은 권장하지 않습니다. 다음 대안 중 하나를 고려하십시오.
open-in-new 대안 비교
비교 대상 장치와 유사한 기능
SN65LVDT388A 활성 8진 LVDS 리시버 This is a newer generation of this product

제품 상세 정보

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 8 Supply voltage (V) 3.3 Signaling rate (MBits) 630 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 8 Supply voltage (V) 3.3 Signaling rate (MBits) 630 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DBT) 38 62.08 mm² 9.7 x 6.4
  • Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
  • Integrated 110- Line Termination Resistors on LVDT Products
  • Designed for Signaling Rates Up To 630 Mbps
  • SN65 Version's Bus-Terminal ESD Exceeds 15 kV
  • Operates From a Single 3.3-V Supply
  • Propagation Delay Time of 2.6 ns (Typ)
  • Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns
  • LVTTL Levels Are 5-V Tolerant
  • Open-Circuit Fail Safe
  • Flow-Through Pin Out
  • Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch

Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

  • Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
  • Integrated 110- Line Termination Resistors on LVDT Products
  • Designed for Signaling Rates Up To 630 Mbps
  • SN65 Version's Bus-Terminal ESD Exceeds 15 kV
  • Operates From a Single 3.3-V Supply
  • Propagation Delay Time of 2.6 ns (Typ)
  • Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns
  • LVTTL Levels Are 5-V Tolerant
  • Open-Circuit Fail Safe
  • Flow-Through Pin Out
  • Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch

Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

The \x91LVDS388 and \x91LVDT388 (T designates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight differential receivers will provide a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT product eliminates this external resistor by integrating it with the receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over 150 million data transfers per second in single-edge clocked systems are possible with very little power. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS388 and SN65LVDT388 is characterized for operation from -40°C to 85°C. The SN75LVDS388 and SN75LVDT388 is characterized for operation from 0°C to 70°C.

The \x91LVDS388 and \x91LVDT388 (T designates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight differential receivers will provide a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT product eliminates this external resistor by integrating it with the receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over 150 million data transfers per second in single-edge clocked systems are possible with very little power. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS388 and SN65LVDT388 is characterized for operation from -40°C to 85°C. The SN75LVDS388 and SN75LVDT388 is characterized for operation from 0°C to 70°C.

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기술 자료

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* Data sheet High-Speed Differential Line Receivers datasheet (Rev. A) 2001/06/01

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시뮬레이션 툴

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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TSSOP (DBT) 38 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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