SN74AUP1G08-Q1
- AEC-Q100 Qualified with the Following Results:
- Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
- Available in the Texas Instruments NanoStar Package
- Low Static-Power Consumption:
ICC = 0.9 µA Max - Low Dynamic-Power Consumption:
Cpd = 4.3 pF Typ at 3.3 V - Low Input Capacitance: Ci = 1.5 pF Typ
- Low Noise: Overshoot and Undershoot
< 10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and Better
Switching Noise Immunity at the Input (Vhys = 250 mV, Typ at
3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V Input/Output (I/O) Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.3 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD-78, Class II
NanoStar is a trademark of Texas Instruments.
The AUP family is TIs premier solution to the low-power needs of the industry in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
This single 2-input positive-AND gate performs the Boolean function: Y = A B or Y = A\ + B\ in positive logic.
NanoStar package technology is a major breakthrough in integrated circuit (IC) packaging concepts, because it uses the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | LOW-POWER SINGLE 2-INPUT POSITIVE AND GATE datasheet | 2012/12/12 | |
Selection guide | Little Logic Guide 2018 (Rev. G) | 2018/07/06 | ||
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | How to Select Little Logic (Rev. A) | 2016/07/26 | ||
More literature | Automotive Logic Devices Brochure | 2014/08/27 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
SOT-SC70 (DCK) | 5 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치