首頁 微控制器 (MCU) 與處理器 微處理器和 DSP 音訊與雷達 DSP SoC
首頁
微控制器 (MCU) 與處理器
微處理器和 DSP
音訊與雷達 DSP SoC

DRA74P

現行

具有 ISP 並與 DRA74x SoC 處理器針腳相容的多核心 SoC 處理器

立即訂購
產品規格表
使用指南

DRA74P

現行
立即訂購

產品詳細資料

CPU 2 Arm Cortex-A15 Frequency (MHz) 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 1 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image system processor, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A15 Frequency (MHz) 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 1 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image system processor, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCCSP (ABZ) 760 529 mm² (23 mm × 23 mm)
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Real-Time Clock Subsystem (RTCSS)
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Real-Time Clock Subsystem (RTCSS)
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.
filter 尋找其它 音訊與雷達 DSP SoC
下載 觀看有字幕稿的影片 影片

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 41
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 DRA75xP, DRA74xP Infotainment Applications Processor Silicon Revision 1.0 datasheet (Rev. F) PDF | HTML 2018/12/10
* 使用指南 DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D) PDF | HTML 2024/5/25
* 勘誤表 TDA2P, DRA7xxP, AM574x Package Discontinued and Redesigned (Rev. B) PDF | HTML 2026/5/26
* 勘誤表 DRA7xx Silicon Errata (Rev. B) PDF | HTML 2024/9/8
應用說明 Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021/5/5
更多文件說明 Building your application with security in mind (Rev. E) 2020/10/28
應用說明 IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020/8/24
應用說明 AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020/1/6
應用說明 Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019/6/11
應用說明 Achieving Early CAN Response on DRA7xx Devices 2018/11/28
應用說明 DRA74x_75x/DRA72x Performance (Rev. A) 2018/10/31
應用說明 Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018/9/14
應用說明 The Implementation of YUV422 Output for SRV 2018/8/2
應用說明 MMC DLL Tuning (Rev. B) 2018/7/31
應用說明 Integrating AUTOSAR on TI SoC: Fundamentals 2018/6/18
應用說明 ECC/EDC on TDAxx (Rev. B) 2018/6/13
應用說明 Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018/6/12
應用說明 Sharing VPE Between VISIONSDK and PSDKLA 2018/5/4
應用說明 Android Boot Optimization on DRA7xx Devices (Rev. A) 2018/2/13
應用說明 Flashing Utility - mflash 2018/1/9
應用說明 Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017/11/30
應用說明 Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017/11/7
應用說明 A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017/11/3
應用說明 Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017/9/12
應用說明 Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017/8/14
應用說明 Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017/7/12
白皮書 Revolutionize the automotive cockpit 2017/6/2
應用說明 Linux Boot Time Optimizations on DRA7xx Devices 2017/3/31
應用說明 Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017/2/17
應用說明 Early Splash Screen on DRA7x Devices 2017/1/31
應用說明 Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016/12/15
應用說明 Gstreamer Migration Guidelines 2016/4/26
使用指南 Jacinto6 Android Video Encoder Software Design Specification User's Guide 2016/4/21
使用指南 Jacinto6 Android Video Decoder Software Design Specification User's Guide 2016/4/21
應用說明 Flashing Binaries to DRA7xx Factory Boards Using DFU 2016/4/14
應用說明 Tools and Techniques for Audio Debugging 2016/4/13
應用說明 Debugging Tools and Techniques With IPC3.x 2016/3/30
應用說明 Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016/1/15
白皮書 Informational ADAS as Software Upgrade to Today’s Infotainment Systems 2014/10/14
應用說明 Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014/8/13
白皮書 Today’s high-end infotainment soon becoming mainstream 2014/6/2

設計與開發

電源供應解決方案

為 DRA74P 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

檢視解決方案
開發板

J6PEVM577P — DRA7xP 評估模組

DRA77xP/DRA76xP-ACD 是一個評估平台，旨在允許擴充性及重複使用 DRA77xP 及 DRA76xP JacintoTM 資訊娛樂系統單晶片 (SoC)。其以 Jacinto DRA77xP SoC 為基礎，結合異質可擴充架構，其中混合了兩個 ARM Cortex-A15 微處理器單元、兩個 Arm® Cortex®-M4 處理子系統、每個子系統配備兩個 ARM Cortex 微處理器、兩個數位訊號處理器 (DSPC66x)、一個內含兩個嵌入式視覺引擎 (EVE) 的視覺加速 Pac、2D 和 3D 圖形處理單元（包括 Imagination Technologies 的 (...)

使用指南: PDF
從：SVTRONICS INC
支援產品和硬體
軟體開發套件 (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
支援產品和硬體
支援軟體

VCTR-3P-MICROSAR — 適用於微控制器和高性能電腦 (HPC) 的 Vector MICROSAR AUTOSAR 軟體

MICROSAR 與 DaVinci 產品系列透過適用於微控制器與 HPC 的精密嵌入式軟體和強大開發工具，簡化 ECU 開發。有了先進的基礎架構軟體，您即可為 ECU 建立最佳基礎，並利用相關工具簡化所有相關開發作業。MICROSAR 嵌入式軟體是根據 AUTOSAR 經典和適應性等相關標準所開發。軟體也適合符合最高 ASIL D 之 ISO 26262 標準的安全相關應用。此外，智慧網路安全功能可保護控制單元免受未經授權的存取和竄改。Vector 涵蓋所有汽車與其他工業應用的使用案例。對於配備高性能電腦的軟體定義車輛 (SDV)，其可提供現代車輛作業系統，以做為開放式模組化軟體生態系統。

從：Vector Informatik GmbH
支援產品和硬體
模擬型號

DRA7xxP and TDA2Px BSDL Files

SPRM750.ZIP (34 KB) - BSDL 模型
支援產品和硬體
模擬型號

DRA7xxP and TDA2Px IBIS Files

SPRM748.ZIP (36622 KB) - IBIS 模型
支援產品和硬體
模擬型號

DRA7xxP and TDA2Px Thermal Model

SPRM749.ZIP (2 KB) - 熱模型
支援產品和硬體
計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCCSP (ABZ) 760 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片