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微控制器 (MCU) 與處理器
微處理器和 DSP
音訊與雷達 DSP SoC

DRA710

現行

適用於資訊娛樂系統與儀錶板，且含繪圖的 600 MHz ARM Cortex-A15 SoC 處理器

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產品規格表
勘誤表

DRA710

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A15 Frequency (MHz) 600 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D Display type 1 HDMI, 2 LCD Protocols Ethernet, ICSS, Profibus PCIe 2 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 1 Arm Cortex-A15 Frequency (MHz) 600 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D Display type 1 HDMI, 2 LCD Protocols Ethernet, ICSS, Profibus PCIe 2 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCCSP (CBD) 538 289 mm² 17 x 17
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.
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技術文件

star =TI 所選的此產品重要文件
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重要文件 類型 標題 格式選項 日期
* Data sheet DRA71x Infotainment Applications Processor datasheet (Rev. G) PDF | HTML 2019年 11月 25日
* Errata DRA72x and DRA71x SoC for Automotive Infortainment Silicon Errata (Rev. F) PDF | HTML 2024年 9月 8日
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021年 5月 5日
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020年 8月 24日
White paper Jump Start Upgrading Your Digital Cluster Design with Jacinto 6 Platform (Rev. A) 2020年 8月 17日
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020年 1月 6日
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019年 6月 11日
User guide DRA71x and DRA72x Technical Reference Manual (Rev. D) 2019年 5月 21日
Application note Achieving Early CAN Response on DRA7xx Devices 2018年 11月 28日
Application note DRA74x_75x/DRA72x Performance (Rev. A) 2018年 10月 31日
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018年 9月 14日
Application note The Implementation of YUV422 Output for SRV 2018年 8月 2日
Application note MMC DLL Tuning (Rev. B) 2018年 7月 31日
Application note Integrating AUTOSAR on TI SoC: Fundamentals 2018年 6月 18日
Application note ECC/EDC on TDAxx (Rev. B) 2018年 6月 13日
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018年 6月 12日
Application note Sharing VPE Between VISIONSDK and PSDKLA 2018年 5月 4日
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 2018年 2月 13日
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017年 11月 30日
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 2017年 11月 27日
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017年 11月 7日
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017年 11月 3日
User guide DRA71x Cost Effective Automotive Reference Design 2017年 11月 1日
Technical article Automotive gateways: the bridge between communication domains PDF | HTML 2017年 9月 20日
Application note Robust Rear-View Camera (RVC) App Report 2017年 9月 13日
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017年 9月 12日
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017年 8月 14日
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017年 7月 12日
Application note Linux Boot Time Optimizations on DRA7xx Devices 2017年 3月 31日
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017年 2月 17日
Application note Early Splash Screen on DRA7x Devices 2017年 1月 31日
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016年 12月 15日
Application note Gstreamer Migration Guidelines 2016年 4月 26日
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide 2016年 4月 21日
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide 2016年 4月 21日
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 2016年 4月 14日
Application note Tools and Techniques for Audio Debugging 2016年 4月 13日
Application note Debugging Tools and Techniques With IPC3.x 2016年 3月 30日
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016年 1月 15日
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 2014年 10月 14日
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014年 8月 13日
White paper Today’s high-end infotainment soon becoming mainstream 2014年 6月 2日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

DRA71XEVM — DRA71x 評估模組

Jacinto™ DRA71x evaluation module (EVM) is an evaluation platform designed to speed up development efforts and reduce time-to-market for applications such as infotainment, reconfigurable digital cluster, or integrated digital cockpit. To allow scalability and reuse across Jacinto DRA71x (...)

使用指南: PDF
View Options
軟體開發套件 (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

支援產品和硬體

支援產品和硬體
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

支援產品和硬體

支援產品和硬體
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

支援產品和硬體

支援產品和硬體
下載選項
IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

支援產品和硬體

支援產品和硬體
啟動 下載選項
作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
從：Green Hills Software
造訪合作夥伴網站
支援軟體

VCTR-3P-MICROSAR — 適用於微控制器和高性能電腦 (HPC) 的 Vector MICROSAR AUTOSAR 軟體

MICROSAR 與 DaVinci 產品系列透過適用於微控制器與 HPC 的精密嵌入式軟體和強大開發工具，簡化 ECU 開發。有了先進的基礎架構軟體，您即可為 ECU 建立最佳基礎，並利用相關工具簡化所有相關開發作業。MICROSAR 嵌入式軟體是根據 AUTOSAR 經典和適應性等相關標準所開發。軟體也適合符合最高 ASIL D 之 ISO 26262 標準的安全相關應用。此外，智慧網路安全功能可保護控制單元免受未經授權的存取和竄改。Vector 涵蓋所有汽車與其他工業應用的使用案例。對於配備高性能電腦的軟體定義車輛 (SDV)，其可提供現代車輛作業系統，以做為開放式模組化軟體生態系統。
從：Vector Informatik GmbH
View Options
模擬型號

DRA71x and DRA79x BSDL Model (Rev. A)

SPRM695A.ZIP (15 KB) - BSDL Model
下載
模擬型號

DRA71x and DRA79x IBIS Model

SPRM697.ZIP (9618 KB) - IBIS Model
下載
模擬型號

DRA71x and DRA79x Thermal Model

SPRM696.ZIP (2 KB) - Thermal Model
下載
計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
View Options
參考設計

TIDA-01425 — 具有乙太網路和 CAN 的車用獨立閘道參考設計

TIDA-01425 為適合汽車閘道的子系統參考設計，著重於增加閘道應用的頻寬與處理能力。此設計採用乙太網路實體層收發器 (PHY) 以增加頻寬，並搭載汽車處理器以提供更優異的處理能力，讓汽車閘道能以更快的速度傳遞更多資料。此外，此設計也提供完整汽車閘道設計的起點，並具備完整電源樹狀結構、CAN PHY 和根據汽車要求和排放規格所選元件，以簡化設計程序。
Design guide: PDF
電路圖: PDF
參考設計

TIDEP-0097 — 採用 Jacinto™ 6 入門級的入門級音響主機參考設計

此車用參考設計以 TI 的 Jacinto™ DRA71x 處理器為基礎，著重於節省系統級成本。其 6 層設計透過斷路方案最佳化、主要功能整合和配電網路最佳化降低 PCB 成本。可根據終端產品需求擴充或移除功能。此設計專為資訊娛樂和可重新設定的數位叢集等應用而設計，並支援 HDMI、USB3.0/2.0、TAS6424 數位 D 類放大器、FPD-Link 介面及多種其他功能。其中包含具單一 PMIC 的 12V 輸入。此外還隨附 Linux、Android 或 QNX 架構的軟體開發套件。
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCCSP (CBD) 538 Ultra Librarian
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  • 認證摘要
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