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LVDS、M-LVDS 和 PECL IC

DS40MB200

現行

具發射預強調和接收等化功能的雙 4.0 Gbps 2:1/1:2 CML 多工器/緩衝器

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DS40MB200

現行
產品規格表 立即訂購

產品詳細資料

Function Equalizer, Mux buffer Protocols CML, LVDS, LVPECL Number of transmitters 2, 4 Number of receivers 2, 4 Supply voltage (V) 3.3 Signaling rate (MBits) 4000 Input signal CML Output signal CML Rating Catalog Operating temperature range (°C) 0 to 85
Function Equalizer, Mux buffer Protocols CML, LVDS, LVPECL Number of transmitters 2, 4 Number of receivers 2, 4 Supply voltage (V) 3.3 Signaling rate (MBits) 4000 Input signal CML Output signal CML Rating Catalog Operating temperature range (°C) 0 to 85
WQFN (NJU) 48 49 mm² 7 x 7
  • 1-Gbps to 4-Gbps Low Jitter Operation
  • Fixed Input Equalization
  • Programmable Output Pre-Emphasis
  • Independent Switch and Line Side Pre-Emphasis
    Controls
  • Programmable Switch-Side Loopback Mode
  • On-Chip Terminations
  • 3.3-V Supply
  • ESD Rating of 6-kV HBM
  • 48-leadless WQFN Package (7 mm × 7 mm)
  • 0°C to +85°C Operating Temperature Range
  • 1-Gbps to 4-Gbps Low Jitter Operation
  • Fixed Input Equalization
  • Programmable Output Pre-Emphasis
  • Independent Switch and Line Side Pre-Emphasis
    Controls
  • Programmable Switch-Side Loopback Mode
  • On-Chip Terminations
  • 3.3-V Supply
  • ESD Rating of 6-kV HBM
  • 48-leadless WQFN Package (7 mm × 7 mm)
  • 0°C to +85°C Operating Temperature Range

The DS40MB200 device is a dual signal conditioning 2:1 multiplexer (MUX) and 1:2 fan-out buffer designed for use in backplane-redundancy applications. Signal conditioning features include continuous time linear equalization (CTLE) and programmable output pre-emphasis, extending data communication in FR4 backplanes at rates up to 4 Gbps. Each input stage has a fixed equalizer to reduce intersymbol interference distortion from board traces.

All output drivers have four selectable steps of pre-emphasis to compensate for transmission losses from long FR4 backplanes and reduce deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100-Ω differential terminating resistors. All drivers are internally terminated with 50 Ω to VCC.

The DS40MB200 device is a dual signal conditioning 2:1 multiplexer (MUX) and 1:2 fan-out buffer designed for use in backplane-redundancy applications. Signal conditioning features include continuous time linear equalization (CTLE) and programmable output pre-emphasis, extending data communication in FR4 backplanes at rates up to 4 Gbps. Each input stage has a fixed equalizer to reduce intersymbol interference distortion from board traces.

All output drivers have four selectable steps of pre-emphasis to compensate for transmission losses from long FR4 backplanes and reduce deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100-Ω differential terminating resistors. All drivers are internally terminated with 50 Ω to VCC.
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類型 標題 日期
* Data sheet DS40MB200 Dual 4-Gbps 2:1/1:2 CML MUX/Buffer With Transmit Pre-Emphasis and Receive Equalization datasheet (Rev. J) PDF | HTML 2015年 10月 14日
Application note AN-1398 Printed Circuit Board Design Techniques for DS40MB200 (Rev. A) 2013年 4月 26日
Application note Driving Signals Over XAUI Backplanes Using DS42MB100, DS40MB200, or DS42BR400 (Rev. B) 2013年 4月 26日
Application note Enabling Redundancy in Multi-Gigabit Links w/DS40MB200 Mux/Buffer (Rev. A) 2013年 4月 26日
Application note Setting Pre-Empha Level for DS40MB200 Dual 4Gb/s Mux/Buffer (Rev. C) 2013年 4月 26日

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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