LM5111

現行

具高電位作動或低輸出 4-V UVLO 的 5-A/3-A 雙通道閘極驅動器

產品詳細資料

Number of channels 2 Power switch MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 3.5 Input supply voltage (max) (V) 14 Features UVLO Configured to Drive PFET through OUT_A Operating temperature range (°C) -40 to 125 Rise time (ns) 14 Fall time (ns) 12 Propagation delay time (µs) 0.025 Input threshold TTL Channel input logic Combination, Inverting, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (typ) (V) 3 Driver configuration Dual, Independent
Number of channels 2 Power switch MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 3.5 Input supply voltage (max) (V) 14 Features UVLO Configured to Drive PFET through OUT_A Operating temperature range (°C) -40 to 125 Rise time (ns) 14 Fall time (ns) 12 Propagation delay time (µs) 0.025 Input threshold TTL Channel input logic Combination, Inverting, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (typ) (V) 3 Driver configuration Dual, Independent
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Independently Drives Two N-Channel MOSFETs
  • Compound CMOS and Bipolar Outputs Reduce Output Current Variation
  • 5-A Sink and 3-A Source Current Capability
  • Two Channels can be Connected in Parallel to Double the Drive Current
  • Independent Inputs (TTL Compatible)
  • Fast Propagation Times (25 ns Typical)
  • Fast Rise and Fall Times (14 ns and 12 ns Rise and Fall, Respectively, With 2-nF Load)
  • Available in Dual Noninverting, Dual Inverting and Combination Configurations
  • Supply Rail Undervoltage Lockout Protection (UVLO)ƒ
  • LM5111-4 UVLO Configured to Drive PFET through OUT_A and NFET through OUT_B
  • Pin Compatible With Industry Standard Gate Drivers
  • Independently Drives Two N-Channel MOSFETs
  • Compound CMOS and Bipolar Outputs Reduce Output Current Variation
  • 5-A Sink and 3-A Source Current Capability
  • Two Channels can be Connected in Parallel to Double the Drive Current
  • Independent Inputs (TTL Compatible)
  • Fast Propagation Times (25 ns Typical)
  • Fast Rise and Fall Times (14 ns and 12 ns Rise and Fall, Respectively, With 2-nF Load)
  • Available in Dual Noninverting, Dual Inverting and Combination Configurations
  • Supply Rail Undervoltage Lockout Protection (UVLO)ƒ
  • LM5111-4 UVLO Configured to Drive PFET through OUT_A and NFET through OUT_B
  • Pin Compatible With Industry Standard Gate Drivers

The LM5111 Dual Gate Driver replaces industry standard gate drivers with improved peak output current and efficiency. Each compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 5-A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Undervoltage lockout protection is also provided. The drivers can be operated in parallel with inputs and outputs connected to double the drive current capability. This device is available in the SOIC package or the thermally enhanced
MSOP-PowerPAD package.

The LM5111 Dual Gate Driver replaces industry standard gate drivers with improved peak output current and efficiency. Each compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 5-A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Undervoltage lockout protection is also provided. The drivers can be operated in parallel with inputs and outputs connected to double the drive current capability. This device is available in the SOIC package or the thermally enhanced
MSOP-PowerPAD package.

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類型 標題 日期
* Data sheet LM5111 Dual 5-A Compound Gate Driver datasheet (Rev. H) PDF | HTML 2016年 9月 28日
Application note Why use a Gate Drive Transformer? PDF | HTML 2024年 3月 4日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Application note Improving Efficiency of DC-DC Conversion through Layout 2019年 5月 7日
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 2018年 10月 29日
Selection guide Power Management Guide 2018 (Rev. R) 2018年 6月 25日
EVM User's guide AN-1937 LM3433 10A to 40A LED Driver Evaluation Board (Rev. D) 2013年 5月 3日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

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使用指南: PDF
TI.com 無法提供
模擬型號

LM5111-1M TINA-TI Transient Reference Design

SNVM404.TSC (146 KB) - TINA-TI Reference Design
模擬型號

LM5111-1M TINA-TI Transient Spice Model

SNVM405.ZIP (9 KB) - TINA-TI Spice Model
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LM5111-2M TINA-TI Transient Reference Design

SNVM411.TSC (147 KB) - TINA-TI Reference Design
模擬型號

LM5111-2M TINA-TI Transient Spice Model

SNVM410.ZIP (10 KB) - TINA-TI Spice Model
模擬型號

LM5111-3M TINA-TI Transient Reference Design

SNVM414.TSC (152 KB) - TINA-TI Reference Design
模擬型號

LM5111-3M TINA-TI Transient Spice Model

SNVM415.ZIP (10 KB) - TINA-TI Spice Model
模擬型號

LM5111-4M TINA-TI Transient Reference Design

SNVM402.TSC (148 KB) - TINA-TI Reference Design
模擬型號

LM5111-4M TINA-TI Transient Spice Model

SNVM403.ZIP (9 KB) - TINA-TI Spice Model
模擬型號

LM5111_1M PSpice Transient Model

SNVM358.ZIP (55 KB) - PSpice Model
模擬型號

LM5111_1M Unencrypted PSpice Transient Model

SNVMAD2.ZIP (1 KB) - PSpice Model
模擬型號

LM5111_2M PSpice Transient Model

SNVM360.ZIP (45 KB) - PSpice Model
模擬型號

LM5111_2M Unencrypted PSpice Transient Model

SNVMAD5.ZIP (1 KB) - PSpice Model
模擬型號

LM5111_3M PSpice Transient Model

SNVM359.ZIP (44 KB) - PSpice Model
模擬型號

LM5111_3M Unencrypted PSpice Transient Model

SNVMAD3.ZIP (1 KB) - PSpice Model
模擬型號

LM5111_4M PSpice Transient Model

SNVM357.ZIP (44 KB) - PSpice Model
模擬型號

LM5111_4M Unencrypted PSpice Transient Model

SNVMAD4.ZIP (1 KB) - PSpice Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計

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Design guide: PDF
電路圖: PDF
封裝 引腳 下載
HVSSOP (DGN) 8 檢視選項
SOIC (D) 8 檢視選項

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